diff --git a/sim/imperas.ic b/sim/imperas.ic
index 5de5935c6..b35166429 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -37,6 +37,8 @@
 # SV39 and SV48 supported
 --override cpu/Sv_modes=768
 
+--override cpu/Svinval=T
+
 
 #  clarify
 #--override refRoot/cpu/mtvec_sext=F
diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S
index dcf56e14a..39b3a8aeb 100644
--- a/tests/coverage/priv.S
+++ b/tests/coverage/priv.S
@@ -300,6 +300,8 @@ sretdone:
 
 
     # Test uncovered privdec instructions
+    li a0, 3
+    ecall
     # exercise sfence.inval.ir instruction
     .word 0x18100073
 
@@ -307,7 +309,20 @@ sretdone:
     .word 0x102F8073
 
 
-    j done
+    # cover mret when mpp = 3 and mprv = 1
+    li a0, 3
+    ecall               # enter machine mode
+    bseti t0, zero, 17
+    csrs mstatus, t0    # set MPRV
+    li t1, 0x00001800   
+    csrs mstatus, t1    # set MPP=3
+    la t1, finished
+    csrr t0, mepc       
+    csrw mepc, t1       # set mepc for mret to jump to
+    mret
+
+
+finished: j done