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Clean up unused signals

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This commit is contained in:
David Harris 2024-06-18 08:07:14 -07:00
parent c1fd7a9589
commit cb563e8018
15 changed files with 25 additions and 43 deletions
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6
src/cache/cache.sv vendored
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@ -87,14 +87,13 @@ module cache import cvw::*; #(parameter cvw_t P,
logic LineDirty, HitLineDirty;
logic [TAGLEN-1:0] TagWay [NUMWAYS-1:0];
logic [TAGLEN-1:0] Tag;
logic [SETLEN-1:0] FlushAdr, NextFlushAdr, FlushAdrP1;
logic [SETLEN-1:0] FlushAdr;
logic FlushAdrCntEn, FlushCntRst;
logic FlushAdrFlag, FlushWayFlag;
logic [NUMWAYS-1:0] FlushWay, NextFlushWay;
logic FlushWayCntEn;
logic SelWriteback;
logic LRUWriteEn;
logic ResetOrFlushCntRst;
logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache;
logic SelFetchBuffer;
logic CacheEn;
@ -201,6 +200,9 @@ module cache import cvw::*; #(parameter cvw_t P,
/////////////////////////////////////////////////////////////////////////////////////////////
if (!READ_ONLY_CACHE) begin:flushlogic // D$ can be flushed
logic ResetOrFlushCntRst;
logic [SETLEN-1:0] NextFlushAdr, FlushAdrP1;
// Flush address (line number)
assign ResetOrFlushCntRst = reset | FlushCntRst;
flopenr #(SETLEN) FlushAdrReg(clk, ResetOrFlushCntRst, FlushAdrCntEn, FlushAdrP1, NextFlushAdr);

1
src/fpu/fdivsqrt/fdivsqrt.sv
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@ -65,7 +65,6 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
logic WZeroE; // Early termination flag
logic [P.DURLEN-1:0] CyclesE; // FSM cycles
logic SpecialCaseM; // Divide by zero, square root of negative, etc.
logic DivStartE; // Enable signal for flops during stall
// Integer div/rem signals
logic BZeroM; // Denominator is zero

2
src/fpu/fdivsqrt/fdivsqrtcycles.sv
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@ -28,9 +28,7 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
input logic [P.FMTBITS-1:0] FmtE,
input logic [P.LOGFLEN-1:0] Nf, // Number of fractional bits in selected format
input logic SqrtE,
input logic IntDivE,
input logic [P.DIVBLEN-1:0] IntResultBitsE,
output logic [P.DURLEN-1:0] CyclesE

6
src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -58,7 +58,6 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
logic [P.DIVBLEN-1:0] mE, ell; // Leading zeros of inputs
logic [P.DIVBLEN-1:0] IntResultBitsE; // bits in integer result
logic NumerZeroE; // Numerator is zero (X or A)
logic AZeroE, BZeroE; // A or B is Zero for integer division
logic SignedDivE; // signed division
logic AsE, BsE; // Signs of integer inputs
@ -96,11 +95,9 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
// Select integer or floating point inputs
mux2 #(P.DIVb+1) ifxmux({Xm, {(P.DIVb-P.NF){1'b0}}}, {PosA, {(P.DIVb-P.XLEN+1){1'b0}}}, IntDivE, IFX);
mux2 #(P.DIVb+1) ifdmux({Ym, {(P.DIVb-P.NF){1'b0}}}, {PosB, {(P.DIVb-P.XLEN+1){1'b0}}}, IntDivE, IFD);
mux2 #(1) numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE);
end else begin // Int not supported
assign IFX = {Xm, {(P.DIVb-P.NF){1'b0}}};
assign IFD = {Ym, {(P.DIVb-P.NF){1'b0}}};
assign NumerZeroE = XZeroE;
end
//////////////////////////////////////////////////////
@ -174,7 +171,6 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
// 4 2(x)-4 = 4(x/2 - 1)) 2(x/2)-4 = 4(x/4 - 1)
// Summary: PreSqrtX = r(x/2or4 - 1)
logic [P.DIVb:0] PreSqrtX;
assign EvenExp = Xe[0] ^ ell[0]; // effective unbiased exponent after normalization is even
mux2 #(P.DIVb+4) sqrtxmux({4'b0,Xnorm[P.DIVb:1]}, {5'b00, Xnorm[P.DIVb:2]}, EvenExp, SqrtX); // X/2 if exponent odd, X/4 if exponent even
@ -215,7 +211,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
// Number of FSM cycles (to FSM)
fdivsqrtcycles #(P) cyclecalc(.FmtE, .Nf, .SqrtE, .IntDivE, .IntResultBitsE, .CyclesE);
fdivsqrtcycles #(P) cyclecalc(.Nf, .IntDivE, .IntResultBitsE, .CyclesE);
if (P.IDIV_ON_FPU) begin:intpipelineregs
logic [P.DIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE;

2
src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
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@ -47,7 +47,7 @@ module fdivsqrtuslc4cmp (
// Wmsbs = | |
logic [6:0] mk2, mk1, mk0, mkm1;
logic [6:0] mkj2, mkj1, mkj0, mkjm1;
logic [6:0] mkj2, mkj1;
logic [6:0] mks2[7:0], mks1[7:0], mks0[7:0], mksm1[7:0];
logic sqrtspecial;

1
src/ieu/bmu/bitmanipalu.sv
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@ -49,7 +49,6 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] ZBBResult; // ZBB Result
logic [P.XLEN-1:0] ZBCResult; // ZBC Result
logic [P.XLEN-1:0] ZBKBResult; // ZBKB Result
logic [P.XLEN-1:0] ZBKCResult; // ZBKC Result
logic [P.XLEN-1:0] ZBKXResult; // ZBKX Result
logic [P.XLEN-1:0] ZKNHResult; // ZKNH Result
logic [P.XLEN-1:0] ZKNDEResult; // ZKNE or ZKND Result

7
src/ieu/bmu/bmuctrl.sv
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@ -33,8 +33,6 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
// Decode stage control signals
input logic [31:0] InstrD, // Instruction in Decode stage
input logic ALUOpD, // Regular ALU Operation
output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
output logic [3:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode?
output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage
output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage
output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage
@ -45,7 +43,6 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
output logic [2:0] ALUSelectD, // ALU select
output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
output logic [3:0] ZBBSelectE, // ZBB mux select signal
output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute
output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage
output logic BMUActiveE // Bit manipulation instruction being executed
);
@ -60,6 +57,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
logic [2:0] BALUControlD; // ALU Control signals for B instructions
logic [2:0] BALUSelectD; // ALU Mux select signal in Decode Stage for BMU operations
logic BALUOpD; // Indicates if it is an ALU B instruction in Decode Stage
logic [3:0] BSelectD; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
logic [3:0] ZBBSelectD; // ZBB mux select signal in Decode stage
`define BMUCTRLW 20
@ -284,5 +283,5 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000);
// BMU Execute stage pipieline control register
flopenrc #(13) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE});
flopenrc #(12) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BALUControlE, BMUActiveE});
endmodule

16
src/ieu/controller.sv
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@ -53,16 +53,13 @@ module controller import cvw::*; #(parameter cvw_t P) (
output logic ALUSrcAE, ALUSrcBE, // ALU operands
output logic ALUResultSrcE, // Selects result to pass on to Memory stage
output logic [2:0] ALUSelectE, // ALU mux select signal
output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit)
output logic [2:0] Funct3E, // Instruction's funct3 field
output logic [6:0] Funct7E, // Instruction's funct7 field
output logic IntDivE, // Integer divide
output logic MDUE, // MDU (multiply/divide) operatio
output logic W64E, // RV64 W-type operation
output logic SubArithE, // Subtraction or arithmetic shift
output logic JumpE, // jump instruction
output logic BranchE, // Branch instruction
output logic SCE, // Store Conditional instruction
output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch)
output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
output logic [3:0] ZBBSelectE, // ZBB mux select signal in Execute stage
@ -81,7 +78,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
output logic CSRReadM, CSRWriteM, PrivilegedM, // CSR read, write, or privileged instruction
output logic [1:0] AtomicM, // Atomic (AMO) instruction
output logic [2:0] Funct3M, // Instruction's funct3 field
output logic RegWriteM, // Instruction writes a register (needed for Hazard unit)
output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
output logic FWriteIntM, // FPU controller writes integer register file
@ -122,6 +118,9 @@ module controller import cvw::*; #(parameter cvw_t P) (
logic FenceXD; // Fence instruction
logic CMOD; // Cache management instruction
logic InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$
logic MemReadE, CSRReadE; // Instruction reads memory, reads a CSR (needed for Hazard unit)
logic MDUE; // MDU (multiply/divide) operatio
logic SCE; // Store Conditional instruction
logic CSRWriteD, CSRWriteE; // CSR write
logic PrivilegedD, PrivilegedE; // Privileged instruction
logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
@ -133,14 +132,12 @@ module controller import cvw::*; #(parameter cvw_t P) (
logic unused;
logic BranchFlagE; // Branch flag to use (chosen between eq or lt)
logic IEURegWriteE; // Register write
logic BRegWriteE; // Register write from BMU controller in Execute Stage
logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers
logic [1:0] AtomicE; // Atomic instruction
logic FenceD, FenceE; // Fence instruction
logic SFenceVmaD; // sfence.vma instruction
logic IntDivM; // Integer divide instruction
logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage
logic [3:0] ZBBSelectD; // ZBB Mux Select Signal
logic RegWriteM; // Instruction writes a register (needed for Hazard unit)
logic [1:0] CZeroD;
logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions
logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions
@ -328,9 +325,9 @@ module controller import cvw::*; #(parameter cvw_t P) (
logic BSubArithD; // TRUE for BMU ext, clr, andn, orn, xnor
logic BALUSrcBD; // BMU alu src select signal
bmuctrl #(P) bmuctrl(.clk, .reset, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD,
bmuctrl #(P) bmuctrl(.clk, .reset, .InstrD, .ALUOpD,
.BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE,
.ALUSelectD(PreALUSelectD), .BSelectE, .ZBBSelectE, .BRegWriteE, .BALUControlE, .BMUActiveE);
.ALUSelectD(PreALUSelectD), .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE);
if (P.ZBA_SUPPORTED) begin
// ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw
assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
@ -356,7 +353,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
// tie off unused bit manipulation signals
assign BSelectE = 4'b0000;
assign BSelectD = 4'b0000;
assign ZBBSelectE = 4'b0000;
assign BALUControlE = 3'b0;
assign BMUActiveE = 1'b0;

1
src/ieu/datapath.sv
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@ -80,7 +80,6 @@ module datapath import cvw::*; #(parameter cvw_t P) (
// Decode stage signals
logic [P.XLEN-1:0] R1D, R2D; // Read data from Rs1 (RD1), Rs2 (RD2)
logic [P.XLEN-1:0] ImmExtD; // Extended immediate in Decode stage
logic [4:0] RdD; // Destination register in Decode stage
// Execute stage signals
logic [P.XLEN-1:0] R1E, R2E; // Source operands read from register file
logic [P.XLEN-1:0] ImmExtE; // Extended immediate in Execute stage

11
src/ieu/ieu.sv
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@ -87,7 +87,6 @@ module ieu import cvw::*; #(parameter cvw_t P) (
logic [2:0] ResultSrcW; // Selects result in Writeback stage
logic ALUResultSrcE; // Selects ALU result to pass on to Memory stage
logic [2:0] ALUSelectE; // ALU select mux signal
logic SCE; // Store Conditional instruction
logic FWriteIntM; // FPU writing to integer register file
logic IntDivW; // Integer divide instruction
logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
@ -101,10 +100,8 @@ module ieu import cvw::*; #(parameter cvw_t P) (
logic [4:0] Rs1D, Rs2D;
logic [4:0] Rs2E; // Source registers
logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers
logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages
logic MemReadE, CSRReadE; // Load, CSRRead instruction
logic RegWriteW; // Register will be written in Writeback stage
logic BranchSignedE; // Branch does signed comparison on operands
logic MDUE; // Multiply/divide instruction
logic BMUActiveE; // Bit manipulation instruction being executed
logic [1:0] CZeroE; // {czero.nez, czero.eqz} instructions active
@ -113,12 +110,12 @@ module ieu import cvw::*; #(parameter cvw_t P) (
.IllegalIEUFPUInstrD, .IllegalBaseInstrD,
.StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, .Rs2E,
.StallE, .FlushE, .FlagsE, .FWriteIntE,
.PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE,
.Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE,
.PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE,
.Funct3E, .Funct7E, .IntDivE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE,
.BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .MDUActiveE,
.FCvtIntE, .ForwardAE, .ForwardBE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
.StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
.RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
.FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM,
.RdW, .RdE, .RdM);

2
src/ifu/ifu.sv
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@ -211,7 +211,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
// delay the interrupt until the LSU is in a clean state.
assign CommittedF = CacheCommittedF | BusCommittedF;
logic IgnoreRequest;
logic IgnoreRequest; // *** unused; RT: is this a bug or delete?
assign IgnoreRequest = ITLBMissF | FlushD;
// The IROM uses untranslated addresses, so it is not compatible with virtual memory.

1
src/lsu/lsu.sv
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@ -131,7 +131,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic [P.LLEN-1:0] DCacheReadDataWordSpillM; // D$ read data
logic [P.LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data
logic [P.LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data
logic [P.LLEN-1:0] ReadDataWordM; // Read data before subword selection
logic [P.LLEN-1:0] ReadDataM; // Final read data
logic [P.XLEN-1:0] IHWriteDataM; // IEU or HPTW write data

4
src/mmu/mmu.sv
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@ -71,7 +71,6 @@ module mmu import cvw::*; #(parameter cvw_t P,
logic PMPStoreAmoAccessFaultM; // Store or AMO access fault from PMP
logic DataMisalignedM; // load or store misaligned
logic Translate; // Translation occurs when virtual memory is active and DisableTranslation is off
logic TLBHit; // Hit in TLB
logic TLBPageFault; // Page fault from TLB
logic ReadNoAmoAccessM; // Read that is not part of atomic operation causes Load faults. Otherwise StoreAmo faults
logic [1:0] PBMemoryType; // PBMT field of PTE during TLB hit, or 00 otherwise
@ -90,12 +89,11 @@ module mmu import cvw::*; #(parameter cvw_t P,
.VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
.PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM,
.DisableTranslation, .PTE, .PageTypeWriteVal,
.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit,
.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss,
.Translate, .TLBPageFault, .UpdateDA, .PBMemoryType);
end else begin:tlb // just pass address through as physical
assign Translate = 1'b0;
assign TLBMiss = 1'b0;
assign TLBHit = 1'b0;
assign TLBPageFault = 1'b0;
assign PBMemoryType = 2'b00;
assign UpdateDA = 1'b0;

2
src/mmu/tlb/tlb.sv
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@ -72,7 +72,6 @@ module tlb import cvw::*; #(parameter cvw_t P,
input logic TLBFlush,
output logic [P.PA_BITS-1:0] TLBPAdr,
output logic TLBMiss,
output logic TLBHit,
output logic Translate,
output logic TLBPageFault,
output logic UpdateDA,
@ -87,6 +86,7 @@ module tlb import cvw::*; #(parameter cvw_t P,
logic [11:0] PTEAccessBits;
logic [1:0] HitPageType;
logic CAMHit;
logic TLBHit;
logic SV39Mode;
logic Misaligned;
logic MegapageMisaligned;

2
src/uncore/spi_apb.sv
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@ -96,7 +96,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel; // unused generic FIFO outputs
/* verilator lint_off UNDRIVEN */
logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
rsrstatetype ReceiveState, ReceiveNextState;
rsrstatetype ReceiveState;
// Transmission signals
logic sck;