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connected drsu in/out in fp-testbench

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testbench gives spurious succesful messages...
check sqrt. result and answer signals are mismatch in waveforms but tb says ok...
This commit is contained in:
Kevin Kim 2023-05-28 21:18:37 -07:00
parent bca32af002
commit caf6840211
4 changed files with 61 additions and 33 deletions
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20
sim/wave-fpu.do
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@ -9,15 +9,15 @@ add wave -noupdate /testbenchfp/Res
add wave -noupdate /testbenchfp/Ans
add wave -noupdate /testbenchfp/DivStart
add wave -noupdate /testbenchfp/FDivBusyE
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/normshift/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/shiftcorrection/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/resultsign/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/round/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/fmashiftcalc/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/divshiftcalc/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/cvtshiftcalc/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/postprocess/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/postprocess/specialcase/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/postprocess/flags/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/postprocess/normshift/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/postprocess/shiftcorrection/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/postprocess/resultsign/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/postprocess/round/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/postprocess/fmashiftcalc/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/postprocess/divshiftcalc/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/postprocess/cvtshiftcalc/*
add wave -group {Testbench} -noupdate /testbenchfp/*
add wave -group {Testbench} -noupdate /testbenchfp/readvectors/*

3
src/fpu/divremsqrt/drsu.sv
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@ -48,7 +48,6 @@ module drsu(
input logic IntDivE, W64E,
input logic [2:0] Frm,
input logic [2:0] OpCtrl,
input logic [`FMTBITS:0] Fmt,
input logic [1:0] PostProcSel,
output logic FDivBusyE, IFDivStartE, FDivDoneE,
output logic [`FLEN-1:0] FResM,
@ -91,7 +90,7 @@ module drsu(
.FlushE, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3M,
.Funct3E, .IntDivE, .FIntDivResultM,
.FDivDoneE, .IFDivStartE);
divremsqrtpostprocess divremsqrtpostprocess(.Xs(XsE), .Ys(YsE), .Xm(XmE), .Ym(YmE), .Frm(Frm), .Fmt(Fmt), .OpCtrl,
divremsqrtpostprocess divremsqrtpostprocess(.Xs(XsE), .Ys(YsE), .Xm(XmE), .Ym(YmE), .Frm(Frm), .Fmt(FmtE), .OpCtrl,
.XZero(XZeroE), .YZero(YZeroE), .XInf(XInfE), .YInf(YInfE), .XNaN(XNaNE), .YNaN(YNaNE), .XSNaN(XSNaNE),
.YSNaN(YSNaNE), .PostProcSel,.DivSticky(DivStickyM), .DivQe(QeM), .DivQm(QmM), .PostProcRes(FResM), .PostProcFlg(FlgM));
endmodule

67
testbench/testbench-fp.sv
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@ -411,7 +411,7 @@ module testbenchfp;
end
end
if (TEST === "divremsqrt") begin // if unified div sqrt is being tested
Tests = {Tests, f128div, f128sqrt};
Tests = {Tests, f64div, f64sqrt};
OpCtrl = {OpCtrl, `DIV_OPCTRL, `SQRT_OPCTRL};
WriteInt = {WriteInt, 1'b0, 1'b0};
for(int i = 0; i<10; i++) begin
@ -531,12 +531,12 @@ module testbenchfp;
end
end
if (TEST === "divremsqrt") begin // if unified div sqrt is being tested
Tests = {Tests, f128div, f128sqrt};
Tests = {Tests, f32div, f32sqrt};
OpCtrl = {OpCtrl, `DIV_OPCTRL, `SQRT_OPCTRL};
WriteInt = {WriteInt, 1'b0, 1'b0};
for(int i = 0; i<10; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'00};
Fmt = {Fmt, 2'b00};
end
end
end
@ -633,14 +633,30 @@ module testbenchfp;
end
end
if (TEST === "divremsqrt") begin // if unified div sqrt is being tested
Tests = {Tests, f128div, f128sqrt};
Tests = {Tests, f16div, f16sqrt};
OpCtrl = {OpCtrl, `DIV_OPCTRL, `SQRT_OPCTRL};
WriteInt = {WriteInt, 1'b0, 1'b0};
for(int i = 0; i<10; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'10};
Fmt = {Fmt, 2'b10};
end
end
if (TEST === "divremsqrttest") begin // if unified div sqrt is being tested
Tests = {Tests, f16sqrt};
OpCtrl = {OpCtrl, `DIV_OPCTRL};
WriteInt = {WriteInt, 1'b0};
for(int i = 0; i<5; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b10};
end
end
if (TEST === "custom") begin // if unified div sqrt is being tested
Tests = {Tests, custom};
OpCtrl = {OpCtrl, `DIV_OPCTRL};
WriteInt = {WriteInt, 1'b0};
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b10};
end
end
@ -718,19 +734,6 @@ module testbenchfp;
.ASticky);
end
if (TEST !=== "divremsqrt") begin : fpostprocess
postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
.OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
.Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss),
.XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE),
.XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE),
.XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
.XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
.FmaASticky(ASticky), .FmaSe(Se),
.FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
.PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
end
if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal),
.XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero,
@ -742,7 +745,7 @@ module testbenchfp;
.Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
.XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
end
if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
if (TEST === "div" | TEST === "sqrt" | TEST === "all" | TEST === "custom") begin: fdivsqrt
fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym),
.XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero),
@ -754,8 +757,30 @@ module testbenchfp;
.Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
.FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));
end
if (TEST === "divremsqrt") begin: divremsqrt
drsu drsu();
if (TEST === "divremsqrt" | TEST === "divremsqrttest") begin: divremsqrt
drsu drsu(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym),
.XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero),
.PostProcSel(UnitVal[1:0]),
.XNaNE(XNaN), .YNaNE(YNaN),
.Frm(FrmVal),
.FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
.StallM(1'b0), .FDivBusyE,
.FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M),
.Funct3E(Funct3E), .IntDivE(1'b0),
.FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE), .FResM(FpRes), .FIntDivResultM(IntRes), .FlgM(Flg));
end
else begin: postprocess
postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
.OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
.Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss),
.XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE),
.XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE),
.XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
.XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
.FmaASticky(ASticky), .FmaSe(Se),
.FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
.PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
end
assign CmpFlg[3:0] = 0;

4
testbench/tests-fp.vh
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@ -581,5 +581,9 @@ string f128fma[] = '{
"f128_mulAdd_rnm.tv"
};
string custom[] = '{
"f16_sqrt_rne.tv"
};