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https://github.com/openhwgroup/cvw
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Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
This commit is contained in:
David Harris
parent
4a4a7b0d03
commit
caedab679a
@ -388,11 +388,10 @@ module testbench;
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end
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end
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// *** 06 January 2024 RT: may have to uncomment this block for vcs/verilator
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integer adrindex;
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if (P.UNCORE_RAM_SUPPORTED)
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always @(posedge clk)
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if (ResetMem) // program memory is sometimes reset
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if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory)
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for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
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dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
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@ -442,6 +441,15 @@ module testbench;
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clk = 1; # 5; clk = 0; # 5;
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end
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/*
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// Print key info each cycle for debugging
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always @(posedge clk) begin
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#2;
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$display("PCM: %x InstrM: %x (%5s) WriteDataM: %x IEUResultM: %x",
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dut.core.PCM, dut.core.InstrM, InstrMName, dut.core.WriteDataM, dut.core.ieu.dp.IEUResultM);
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end
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*/
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////////////////////////////////////////////////////////////////////////////////
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// Support logic
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////////////////////////////////////////////////////////////////////////////////
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@ -504,6 +512,9 @@ module testbench;
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input logic riscofTest;
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input integer begin_signature_addr;
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output integer errors;
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int fd, code;
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string line;
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int siglines, sigentries;
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localparam SIGNATURESIZE = 5000000;
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integer i;
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@ -512,41 +523,48 @@ module testbench;
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string signame;
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logic [P.XLEN-1:0] testadr, testadrNoBase;
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// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
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// clear signature to prevent contamination from previous tests
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for(i=0; i<SIGNATURESIZE; i=i+1) begin
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sig32[i] = 'bx;
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end
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// read .signature.output file and compare to check for errors
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if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
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else signame = {pathname, TestName, ".signature.output"};
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// read signature, reformat in 64 bits if necessary
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$readmemh(signame, sig32);
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i = 0;
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while (i < SIGNATURESIZE) begin
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if (P.XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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end else begin
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signature[i/2] = {sig32[i+1], sig32[i]};
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i = i + 2;
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// read signature file from memory and count lines. Can't use readmemh because we need the line count
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// $readmemh(signame, sig32);
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fd = $fopen(signame, "r");
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siglines = 0;
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if (fd == 0) $display("Unable to read %s", signame);
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else begin
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while (!$feof(fd)) begin
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code = $fgets(line, fd);
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if (!code) begin
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int errno;
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string errstr;
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errno = $ferror(fd, errstr);
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if (errno) $display("Error %d (code %d) reading line %d of %s: %s", errno, code, siglines, signame, errstr);
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end else if (line.len() > 1) begin // skip blank lines
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if ($sscanf(line, "%x", sig32[siglines])) siglines = siglines + 1; // increment if line is not blank
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end
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if (i >= 4 & sig32[i-4] === 'bx) begin
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if (i == 4) begin
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i = SIGNATURESIZE+1; // flag empty file
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$display(" Error: empty test file");
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end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
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end
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$fclose(fd);
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end
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// Check valid number of lines were read
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if (siglines == 0) begin
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errors = 1;
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$display("Error: empty test file %s", signame);
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end else if (P.XLEN == 64 & (siglines % 2)) begin
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errors = 1;
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$display("Error: RV64 signature has odd number of lines %s", signame);
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end else errors = 0;
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// copy lines into signature, converting to XLEN if necessary
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sigentries = (P.XLEN == 32) ? siglines : siglines/2; // number of signature entries
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for (i=0; i<sigentries; i++)
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signature[i] = (P.XLEN == 32) ? sig32[i] : {sig32[i*2+1], sig32[i*2]};
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// Check errors
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errors = (i == SIGNATURESIZE+1); // error if file is empty
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i = 0;
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testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
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testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
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/* verilator lint_off INFINITELOOP */
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/* verilator lint_off WIDTHXZEXPAND */
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while (signature[i] !== 'bx) begin
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/* verilator lint_on WIDTHXZEXPAND */
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for (i=0; i<sigentries; i++) begin
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logic [P.XLEN-1:0] sig;
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// **************************************
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// ***** BUG BUG BUG make sure RT undoes this.
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@ -560,21 +578,12 @@ module testbench;
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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//$display(" Error on test %s result %d: adr = %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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// TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
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$stop; //***debug
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$stop;
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end
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i = i + 1;
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end
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/* verilator lint_on INFINITELOOP */
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if (errors == 0) begin
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$display("%s succeeded. Brilliant!!!", TestName);
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end else begin
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$display("%s failed with %d errors. :(", TestName, errors);
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//totalerrors = totalerrors+1;
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end
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endtask //
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if (errors) $display("%s failed with %d errors. :(", TestName, errors);
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else $display("%s succeeded. Brilliant!!!", TestName);
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endtask
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/* verilator lint_on WIDTHTRUNC */
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/* verilator lint_on WIDTHEXPAND */
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