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Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x

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This commit is contained in:
David Harris 2024-01-07 07:14:12 -08:00
parent 4a4a7b0d03
commit caedab679a
2 changed files with 54 additions and 45 deletions
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93
testbench/testbench.sv
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@ -388,11 +388,10 @@ module testbench;
end end
end end
// *** 06 January 2024 RT: may have to uncomment this block for vcs/verilator
integer adrindex; integer adrindex;
if (P.UNCORE_RAM_SUPPORTED) if (P.UNCORE_RAM_SUPPORTED)
always @(posedge clk) always @(posedge clk)
if (ResetMem) // program memory is sometimes reset if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory)
for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
@ -442,6 +441,15 @@ module testbench;
clk = 1; # 5; clk = 0; # 5; clk = 1; # 5; clk = 0; # 5;
end end
/*
// Print key info each cycle for debugging
always @(posedge clk) begin
#2;
$display("PCM: %x InstrM: %x (%5s) WriteDataM: %x IEUResultM: %x",
dut.core.PCM, dut.core.InstrM, InstrMName, dut.core.WriteDataM, dut.core.ieu.dp.IEUResultM);
end
*/
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Support logic // Support logic
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
@ -504,6 +512,9 @@ module testbench;
input logic riscofTest; input logic riscofTest;
input integer begin_signature_addr; input integer begin_signature_addr;
output integer errors; output integer errors;
int fd, code;
string line;
int siglines, sigentries;
localparam SIGNATURESIZE = 5000000; localparam SIGNATURESIZE = 5000000;
integer i; integer i;
@ -512,41 +523,48 @@ module testbench;
string signame; string signame;
logic [P.XLEN-1:0] testadr, testadrNoBase; logic [P.XLEN-1:0] testadr, testadrNoBase;
// for tests with no self checking mechanism, read .signature.output file and compare to check for errors // read .signature.output file and compare to check for errors
// clear signature to prevent contamination from previous tests
for(i=0; i<SIGNATURESIZE; i=i+1) begin
sig32[i] = 'bx;
end
if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"}; if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
else signame = {pathname, TestName, ".signature.output"}; else signame = {pathname, TestName, ".signature.output"};
// read signature, reformat in 64 bits if necessary
$readmemh(signame, sig32); // read signature file from memory and count lines. Can't use readmemh because we need the line count
i = 0; // $readmemh(signame, sig32);
while (i < SIGNATURESIZE) begin fd = $fopen(signame, "r");
if (P.XLEN == 32) begin siglines = 0;
signature[i] = sig32[i]; if (fd == 0) $display("Unable to read %s", signame);
i = i+1; else begin
end else begin while (!$feof(fd)) begin
signature[i/2] = {sig32[i+1], sig32[i]}; code = $fgets(line, fd);
i = i + 2; if (!code) begin
end int errno;
if (i >= 4 & sig32[i-4] === 'bx) begin string errstr;
if (i == 4) begin errno = $ferror(fd, errstr);
i = SIGNATURESIZE+1; // flag empty file if (errno) $display("Error %d (code %d) reading line %d of %s: %s", errno, code, siglines, signame, errstr);
$display(" Error: empty test file"); end else if (line.len() > 1) begin // skip blank lines
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency if ($sscanf(line, "%x", sig32[siglines])) siglines = siglines + 1; // increment if line is not blank
end
end end
$fclose(fd);
end end
// Check valid number of lines were read
if (siglines == 0) begin
errors = 1;
$display("Error: empty test file %s", signame);
end else if (P.XLEN == 64 & (siglines % 2)) begin
errors = 1;
$display("Error: RV64 signature has odd number of lines %s", signame);
end else errors = 0;
// copy lines into signature, converting to XLEN if necessary
sigentries = (P.XLEN == 32) ? siglines : siglines/2; // number of signature entries
for (i=0; i<sigentries; i++)
signature[i] = (P.XLEN == 32) ? sig32[i] : {sig32[i*2+1], sig32[i*2]};
// Check errors // Check errors
errors = (i == SIGNATURESIZE+1); // error if file is empty
i = 0;
testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8); testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
/* verilator lint_off INFINITELOOP */ for (i=0; i<sigentries; i++) begin
/* verilator lint_off WIDTHXZEXPAND */
while (signature[i] !== 'bx) begin
/* verilator lint_on WIDTHXZEXPAND */
logic [P.XLEN-1:0] sig; logic [P.XLEN-1:0] sig;
// ************************************** // **************************************
// ***** BUG BUG BUG make sure RT undoes this. // ***** BUG BUG BUG make sure RT undoes this.
@ -560,21 +578,12 @@ module testbench;
errors = errors+1; errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
//$display(" Error on test %s result %d: adr = %h sim (DTIM_SUPPORTED) = %h, signature = %h", $stop;
// TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
$stop; //***debug
end end
i = i + 1;
end end
/* verilator lint_on INFINITELOOP */ if (errors) $display("%s failed with %d errors. :(", TestName, errors);
if (errors == 0) begin else $display("%s succeeded. Brilliant!!!", TestName);
$display("%s succeeded. Brilliant!!!", TestName); endtask
end else begin
$display("%s failed with %d errors. :(", TestName, errors);
//totalerrors = totalerrors+1;
end
endtask //
/* verilator lint_on WIDTHTRUNC */ /* verilator lint_on WIDTHTRUNC */
/* verilator lint_on WIDTHEXPAND */ /* verilator lint_on WIDTHEXPAND */

6
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output
View File

@ -13,7 +13,7 @@
00000001 # delay 1 00000001 # delay 1
00080000 # fmt 00080000 # fmt
00000000 # tx_data 00000000 # tx_data
00000000 # tx_mark 00000000 # tx_mark
@ -23,7 +23,7 @@
00000000 # ie reset 00000000 # ie reset
00000000 # ip reset 00000000 # ip reset
00000000 # fifo watermark and edge case tests 00000000 # fifo watermark and edge case tests
00000001 00000001
@ -249,7 +249,7 @@
00000000 #read mip 00000000 #read mip
00000000 #read tx ip 00000000 #read tx ip
00000022 #clear 1 frame from rx fifo 00000022 #clear 1 frame from rx fifo
00000000 # read recieve ip 00000000 # read recieve ip