Merge branch 'main' of https://github.com/openhwgroup/cvw

.gitmodules

@@ -24,3 +24,6 @@
 [submodule "addins/branch-predictor-simulator"]
 	path = addins/branch-predictor-simulator
 	url = https://github.com/synxlin/branch-predictor-simulator.git
+[submodule "addins/FreeRTOS-Kernel"]
+	path = addins/FreeRTOS-Kernel
+	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git

addins/FreeRTOS-Kernel

@@ -0,0 +1 @@
+Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31

sim/FPbuild.txt

@@ -34,18 +34,14 @@ other FP tests given by the great SoftFloat/TestFloat output.
 
 4a.) Each test will test all its vectors - if you want to test a
 subset of the vectors (e.g., only binary16), you should modify the
-cvw/testbench/tests-fp.h and comment out the tests  you do not want to
+testfloat.do in the sim directory.  Change the TEST_SIZE="all" to the
-test.  The best way to do this is to comment out each item out with
+specific test you want to run.  For example, if you want to run only
-the // comment option in SV.  For example,
+binary16, you should set this variable to TEST_SIZE="HP".
-
-string f128div[] = '{
-//	"f128_div_rne.tv",
-//	"f128_div_rz.tv",
-//	"f128_div_ru.tv",
-//	"f128_div_rd.tv",
-//	"f128_div_rnm.tv"
-};
 
+4b.) If you want to turn off the generation of wlf files while running
+sim-testfloat-batch, you can modify testfloat.do in the sim
+directory.  Inside this DO file, modify the WAV file to 0 --> i.e.,
+set "quietly set WAV 0;"
 
 
 

sim/sim-testfloat-batch

@@ -10,6 +10,4 @@
 # sqrt   - test square root
 # all    - test everything
 
-# nowave for 2nd argument supresses wlf files
+vsim -c -do "do testfloat.do rv64fpquad $1"
-
-vsim -c -do "do testfloat.do rv64fpquad $1 $2"

sim/testfloat.do

@@ -25,14 +25,18 @@ vlib work
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 # $num = the added words after the call
-vlog +incdir+../config/$1 +incdir+../config/shared ../src/wally/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
+vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
 
-vsim -voptargs=+acc work.testbenchfp -G TEST=$2
+# Change TEST_SIZE to only test certain FP width
+# values are QP, DP, SP, HP
+vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all" 
 
-# Determine if nowave argument is provided
+# Set WAV variable to avoid having any output to wave (to limit disk space)
-#   this removes any output to a wlf or wave window to reduce
+quietly set WAV 1;
-#   disk space.
+
-if {($argc > 2) && ($3 eq "nowave")} {
+# Determine if nowave argument is provided this removes any output to
+# a wlf or wave window to reduce disk space.
+if {$WAV eq 0} {
     puts "No wave output is selected"
 } else {
     puts "wave output is selected"

sim/wave-fpu.do

@@ -9,6 +9,12 @@ add wave -noupdate /testbenchfp/Res
 add wave -noupdate /testbenchfp/Ans
 add wave -noupdate /testbenchfp/DivStart
 add wave -noupdate /testbenchfp/FDivBusyE
+add wave -noupdate /testbenchfp/CheckNow
+add wave -noupdate /testbenchfp/DivDone
+add wave -noupdate /testbenchfp/ResMatch
+add wave -noupdate /testbenchfp/FlagMatch
+add wave -noupdate /testbenchfp/CheckNow
+add wave -noupdate /testbenchfp/NaNGood
 add wave -group {PostProc} -noupdate /testbenchfp/postprocess/*
 add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/*
 add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/*

tests/fp/combined_IF_vectors/extract_arch_vectors.py

@@ -1,7 +1,7 @@
 #! /usr/bin/python3
 
-# author: Alessandro Maiuolo
+# author: Alessandro Maiuolo, Kevin Kim
-# contact: amaiuolo@g.hmc.edu
+# contact: amaiuolo@g.hmc.edu, kekim@hmc.edu
 # date created: 3-29-2023
 
 # extract all arch test vectors
@@ -77,7 +77,7 @@ def create_vectors(my_config):
         rounding_mode = "X"
         flags = "XX"
         # use name to create our new tv
-        dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'a')
+        dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'w')
         # open vectors
         src_file1 = open(source_dir1 + vector1,'r')
         src_file2 = open(source_dir2 + vector2,'r')
@@ -144,7 +144,7 @@ def create_vectors(my_config):
                 answer2 = src_file2.readline().strip()
                 answer1 = src_file2.readline().strip()
                 answer = answer1 + answer2
-                # print(answer1,answer2)
+                #print(answer1,answer2)
                 if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
                     # parse through .S file
                     detected = False
@@ -179,13 +179,56 @@ def create_vectors(my_config):
                 else:
                     # print("read false")
                     reading = False
+        elif my_config.letter == "M" and my_config.bits == 32:
+            reading = True
+            while reading:
+                # print("trigger 64M")
+                # get answer from Ref...signature
+                # answers span two lines and are reversed
+                answer = src_file2.readline().strip()
+                print(f"Answer: {answer}")
+                #print(answer1,answer2)
+                if not (answer == "6f5ca309"): # if there is still stuff to read
+                    # parse through .S file
+                    detected = False
+                    done = False
+                    op1val = "0"
+                    op2val = "0"
+                    while not (detected or done):
+                        # print("det1")
+                        line = src_file1.readline()
+                        # print(line)
+                        if "op1val" in line:
+                            # print("det2")
+                            # parse line
+                            op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
+                            if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
+                                op1val = twos_comp(my_config.bits, op1val)
+                            if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
+                                op2val = line.split("op2val")[1].split("x")[1].strip()
+                                if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
+                                if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
+                                    op2val = twos_comp(my_config.bits, op2val)
+                            # go to next test in vector
+                            detected = True
+                        elif "RVTEST_CODE_END" in line:
+                            done = True
+                    # ints don't have flags
+                    flags = "XX"
+                    # put it all together
+                    if not done:
+                        translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags.strip(), rounding_mode)
+                        dest_file.write(translation + "\n")
+                else:
+                    # print("read false")
+                    reading = False 
         else:
             while reading:
                 # get answer and flags from Ref...signature
                 answer = src_file2.readline()
-                # print(answer)
+                print(answer)
                 packed = src_file2.readline()[6:]
-                # print(packed)
+                print("Packed: ", packed)
                 if len(packed.strip())>0: # if there is still stuff to read
                     # print("packed")
                     # parse through .S file
@@ -229,7 +272,7 @@ def create_vectors(my_config):
         src_file2.close()
 
 config_list = [
-Config(32, "M", "div", "div_", 0),
+Config(32, "M", "div", "div-", 0),
 Config(32, "F", "fdiv", "fdiv", 1),
 Config(32, "F", "fsqrt", "fsqrt", 2),
 Config(32, "M", "rem", "rem-", 3),