diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index b21772e2a..ea7e26d5d 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -76,6 +76,8 @@ module testbench();
       $readmemh(memfilename, dut.uncore.dtim.RAM);
       for(j=2371; j < 65535; j = j+1)
         dut.uncore.dtim.RAM[j] = 64'b0;
+      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr";
+      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab";
       reset = 1; # 22; reset = 0;
     end
   // generate clock to sequence tests
@@ -92,11 +94,16 @@ module testbench();
       end
     end
 
+  if (1 == 1) begin : functionRadix
+    function_radix function_radix(.reset(reset),
+                  .ProgramAddrMapFile(ProgramAddrMapFile),
+                  .ProgramLabelMapFile(ProgramLabelMapFile));
+  end
+
   initial begin
     $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory);
     $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
   end
-
    
 endmodule
 /* verilator lint_on STMTDLY */