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https://github.com/openhwgroup/cvw
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Simplifying trap/csr interface
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56c154f2e7
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@ -40,7 +40,7 @@ module csr #(parameter
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input logic FlushE, FlushM, FlushW,
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input logic FlushE, FlushM, FlushW,
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input logic StallE, StallM, StallW,
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input logic StallE, StallM, StallW,
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input logic [31:0] InstrM,
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input logic [31:0] InstrM,
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input logic [`XLEN-1:0] PCM, SrcAM,
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input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM,
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input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, mretM, sretM, wfiM, InterruptM,
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input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, mretM, sretM, wfiM, InterruptM,
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input logic MTimerInt, MExtInt, SExtInt, MSwInt,
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input logic MTimerInt, MExtInt, SExtInt, MSwInt,
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input logic [63:0] MTIME_CLINT,
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input logic [63:0] MTIME_CLINT,
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@ -55,7 +55,7 @@ module csr #(parameter
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input logic ICacheMiss,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic ICacheAccess,
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input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
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input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
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input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
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input logic [`XLEN-1:0] CauseM, //NextFaultMtvalM,
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input logic SelHPTW,
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input logic SelHPTW,
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output logic [1:0] STATUS_MPP,
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output logic [1:0] STATUS_MPP,
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output logic STATUS_SPP, STATUS_TSR, STATUS_TVM,
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output logic STATUS_SPP, STATUS_TSR, STATUS_TVM,
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@ -71,7 +71,7 @@ module csr #(parameter
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input logic [4:0] SetFflagsM,
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input logic [4:0] SetFflagsM,
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output logic [2:0] FRM_REGW,
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output logic [2:0] FRM_REGW,
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output logic [`XLEN-1:0] CSRReadValW,
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output logic [`XLEN-1:0] CSRReadValW, PrivilegedNextPCM,
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output logic IllegalCSRAccessM, BigEndianM
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output logic IllegalCSRAccessM, BigEndianM
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);
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);
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@ -96,10 +96,57 @@ module csr #(parameter
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logic IllegalCSRMWriteReadonlyM;
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logic IllegalCSRMWriteReadonlyM;
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logic [`XLEN-1:0] CSRReadVal2M;
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logic [`XLEN-1:0] CSRReadVal2M;
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logic [11:0] MIP_REGW_writeable;
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logic [11:0] MIP_REGW_writeable;
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logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector, NextFaultMtvalM;
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logic InstrValidNotFlushedM;
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logic InstrValidNotFlushedM;
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assign InstrValidNotFlushedM = ~StallW & ~FlushW;
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assign InstrValidNotFlushedM = ~StallW & ~FlushW;
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///////////////////////////////////////////
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// MTVAL
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///////////////////////////////////////////
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always_comb
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case (CauseM)
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12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint
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2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault
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0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults
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default: NextFaultMtvalM = 0; // Ecall, interrupts
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endcase
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///////////////////////////////////////////
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// Trap Vectoring
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///////////////////////////////////////////
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//
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// POSSIBLE OPTIMIZATION:
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// From 20190608 privielegd spec page 27 (3.1.7)
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// > Allowing coarser alignments in Vectored mode enables vectoring to be
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// > implemented without a hardware adder circuit.
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// For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with
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// [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000}
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// However, this is program dependent, so not implemented at this time.
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always_comb
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if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW;
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else PrivilegedTrapVector = MTVEC_REGW;
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if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
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always_comb
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if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1)
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PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00};
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else
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PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
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end
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else begin
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assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
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end
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always_comb
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if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector;
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else if (mretM) PrivilegedNextPCM = MEPC_REGW;
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else PrivilegedNextPCM = SEPC_REGW;
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// modify CSRs
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// modify CSRs
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always_comb begin
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always_comb begin
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// Choose either rs1 or uimm[4:0] as source
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// Choose either rs1 or uimm[4:0] as source
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@ -81,7 +81,7 @@ module privileged (
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output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM
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output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM
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);
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);
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logic [`XLEN-1:0] CauseM, NextFaultMtvalM;
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logic [`XLEN-1:0] CauseM; //, NextFaultMtvalM;
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logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW;
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logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW;
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logic [`XLEN-1:0] MEDELEG_REGW;
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logic [`XLEN-1:0] MEDELEG_REGW;
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logic [11:0] MIDELEG_REGW;
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logic [11:0] MIDELEG_REGW;
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@ -125,7 +125,7 @@ module privileged (
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csr csr(.clk, .reset,
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csr csr(.clk, .reset,
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.FlushE, .FlushM, .FlushW,
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.FlushE, .FlushM, .FlushW,
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.StallE, .StallM, .StallW,
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.StallE, .StallM, .StallW,
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.InstrM, .PCM, .SrcAM,
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.InstrM, .PCM, .SrcAM, .IEUAdrM,
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.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .mretM, .sretM, .wfiM, .InterruptM,
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.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .mretM, .sretM, .wfiM, .InterruptM,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTIME_CLINT,
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.MTIME_CLINT,
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@ -133,7 +133,7 @@ module privileged (
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
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.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.NextPrivilegeModeM, .PrivilegeModeW,
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.NextPrivilegeModeM, .PrivilegeModeW,
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.CauseM, .NextFaultMtvalM, .SelHPTW,
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.CauseM, /*.NextFaultMtvalM,*/ .SelHPTW,
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.STATUS_MPP,
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.STATUS_MPP,
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.STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
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.STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
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.MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
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.MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
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@ -146,7 +146,7 @@ module privileged (
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.PMPADDR_ARRAY_REGW,
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.PMPADDR_ARRAY_REGW,
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.SetFflagsM,
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.SetFflagsM,
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.FRM_REGW,
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.FRM_REGW,
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.CSRReadValW,
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.CSRReadValW,.PrivilegedNextPCM,
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.IllegalCSRAccessM, .BigEndianM);
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.IllegalCSRAccessM, .BigEndianM);
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privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
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privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
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@ -164,11 +164,11 @@ module privileged (
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.MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
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.MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
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.MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
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.MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
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.STATUS_MIE, .STATUS_SIE,
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.STATUS_MIE, .STATUS_SIE,
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.PCM, .IEUAdrM, .InstrM,
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/* .PCM, .IEUAdrM, .InstrM,*/
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.InstrValidM, .CommittedM,
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.InstrValidM, .CommittedM,
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.TrapM, .MTrapM, .STrapM, .RetM,
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.TrapM, .MTrapM, .STrapM, .RetM,
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.InterruptM, .IntPendingM,
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.InterruptM, .IntPendingM,
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.PrivilegedNextPCM, .CauseM, .NextFaultMtvalM);
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/* .PrivilegedNextPCM, */.CauseM/*MtvalM*/);
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endmodule
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endmodule
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@ -42,13 +42,13 @@ module trap (
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(* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW,
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(* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW,
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(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
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(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
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input logic STATUS_MIE, STATUS_SIE,
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input logic STATUS_MIE, STATUS_SIE,
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input logic [`XLEN-1:0] PCM,
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/* input logic [`XLEN-1:0] PCM,
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input logic [`XLEN-1:0] IEUAdrM,
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input logic [`XLEN-1:0] IEUAdrM,
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input logic [31:0] InstrM,
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input logic [31:0] InstrM, */
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input logic InstrValidM, CommittedM,
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input logic InstrValidM, CommittedM,
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output logic TrapM, MTrapM, STrapM, RetM,
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output logic TrapM, MTrapM, STrapM, RetM,
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output logic InterruptM, IntPendingM,
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output logic InterruptM, IntPendingM,
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output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
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output logic [`XLEN-1:0] /*PrivilegedNextPCM, */CauseM //NextFaultMtvalM
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// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
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// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
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// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
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// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
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);
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);
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@ -57,7 +57,7 @@ module trap (
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logic ExceptionM;
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logic ExceptionM;
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(* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM;
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(* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM;
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//logic InterruptM;
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//logic InterruptM;
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logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
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//logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
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///////////////////////////////////////////
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///////////////////////////////////////////
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// Determine pending enabled interrupts
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// Determine pending enabled interrupts
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@ -87,6 +87,7 @@ module trap (
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assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
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assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
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assign RetM = mretM | sretM;
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assign RetM = mretM | sretM;
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/*
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always_comb
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always_comb
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if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW;
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if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW;
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else PrivilegedTrapVector = MTVEC_REGW;
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else PrivilegedTrapVector = MTVEC_REGW;
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@ -118,6 +119,7 @@ module trap (
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if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector;
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if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector;
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else if (mretM) PrivilegedNextPCM = MEPC_REGW;
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else if (mretM) PrivilegedNextPCM = MEPC_REGW;
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else PrivilegedNextPCM = SEPC_REGW;
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else PrivilegedNextPCM = SEPC_REGW;
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*/
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///////////////////////////////////////////
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///////////////////////////////////////////
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// Cause priority defined in table 3.7 of 20190608 privileged spec
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// Cause priority defined in table 3.7 of 20190608 privileged spec
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@ -145,17 +147,6 @@ module trap (
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else if (StoreAmoAccessFaultM) CauseM = 7;
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else if (StoreAmoAccessFaultM) CauseM = 7;
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else CauseM = 0;
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else CauseM = 0;
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///////////////////////////////////////////
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// MTVAL
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///////////////////////////////////////////
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always_comb
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case (CauseM)
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12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint
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2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault
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0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults
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default: NextFaultMtvalM = 0; // Ecall, interrupts
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endcase
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/* always_comb
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/* always_comb
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if (InstrPageFaultM) NextFaultMtvalM = PCM;
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if (InstrPageFaultM) NextFaultMtvalM = PCM;
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else if (InstrAccessFaultM) NextFaultMtvalM = PCM;
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else if (InstrAccessFaultM) NextFaultMtvalM = PCM;
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