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Fixed endian swapping on bus only

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This commit is contained in:
David Harris 2022-08-26 19:58:04 -07:00
parent 5f37e16b62
commit ca6837f597
1 changed files with 4 additions and 5 deletions
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9
pipelined/src/lsu/lsu.sv
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@ -250,7 +250,7 @@ module lsu (
assign LSUHADDR = LSUPAdrM;
assign LSUHSIZE = LSUFunct3M;
flopen #(`XLEN) fb(.clk, .en(LSUBusRead), .d(HRDATA), .q(ReadDataWordMuxM));
flopen #(`XLEN) fb(.clk, .en(LSUBusRead), .d(HRDATA), .q(ReadDataWordM));
assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
busfsm #(LOGBWPL) busfsm(
@ -259,12 +259,11 @@ module lsu (
.BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead),
.HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM));
// *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian
assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
assign LSUHBURST = 3'b0;
assign LSUTransComplete = LSUBusAck;
assign {ReadDataWordM, DCacheStallM, DCacheCommittedM} = '0;
assign {DCacheMiss, DCacheAccess} = '0;
end
assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
end
end else begin: nobus // block: bus
assign LSUHWDATA = '0;
assign ReadDataWordMuxM = LittleEndianReadDataWordM;