From ff7dc4f34ae1cf53ae3ffbddd65d5b1046ad2a6d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 7 Feb 2023 15:22:14 -0600 Subject: [PATCH] fpga constraints updates --- fpga/constraints/debug2.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 8b0b7c448..7ea5bf6bd 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -281,7 +281,7 @@ connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/Re create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe54] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] -connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/TrapM ]] +connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/TrapM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe55]