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https://github.com/openhwgroup/cvw
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Merge branch 'main' of github.com:openhwgroup/cvw
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commit
ca1c09041a
7
bin/wsim
7
bin/wsim
@ -89,10 +89,11 @@ if(int(args.locksteplog) >= 1): EnableLog = 1
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else: EnableLog = 0
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prefix = ""
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if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp):
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if (args.sim == "questa" or args.sim == "vcs"):
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if (args.sim == "questa" or args.sim == "vcs"):
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prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic"
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if (args.sim == "questa"):
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prefix = "MTI_VCO_MODE=64 " + prefix
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# Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines
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if (args.sim == "questa"):
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prefix = "MTI_VCO_MODE=64 " + prefix
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if (args.lockstep or args.lockstepverbose):
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if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
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@ -76,7 +76,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
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assign Eeqm1 = ($signed(E) == -1);
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// Logic for nonnegative mask and rounding bits
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assign IMask = {1'b1, {P.NF{1'b0}}} >>> E; /// if E > Nf, this produces all 0s instead of all 1s. Hence exact handling is needed below.
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assign IMask = $signed({1'b1, {P.NF{1'b0}}}) >>> E; /// if E > Nf, this produces all 0s instead of all 1s. Hence exact handling is needed below.
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assign Tmasknonneg = ~IMask >>> 1'b1;
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assign HotE = IMask & ~(IMask << 1'b1);
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assign HotEP1 = HotE >> 1'b1;
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