divremsqrt directory passes lint

src/fpu/divremsqrt/divremsqrtpostprocess.sv

@@ -47,7 +47,7 @@ module divremsqrtpostprocess (
   input logic  [`DIVb:0]                  DivQm,      // divsqrt significand
   // final results
   output logic [`FLEN-1:0]                PostProcRes,// postprocessor final result
-  output logic [4:0]                      PostProcFlg,// postprocesser flags
+  output logic [4:0]                      PostProcFlg // postprocesser flags
   );
   
   // general signals
@@ -163,7 +163,7 @@ module divremsqrtpostprocess (
   ///////////////////////////////////////////////////////////////////////////////
 
   divremsqrtflags flags(.XSNaN, .YSNaN, .XInf, .YInf, .InfIn, .XZero, .YZero, 
-              .Xs, .Sqrt,
+              .Xs, .OutFmt, .Sqrt,
               .NaNIn, .Round, .DivByZero,
               .Guard, .Sticky, .UfPlus1,.DivOp, .FullRe, .Plus1,
               .Me, .Invalid, .Overflow, .PostProcFlg);

src/fpu/divremsqrt/divremsqrtround.sv

@@ -36,7 +36,7 @@
 //  single and double will always be smaller than XLEN
 `define XLENPOS ((`XLEN>`NF) ? 1 : (`XLEN>`NF1) ? 2 : 3)
 
-module round(
+module divremsqrtround(
   input  logic [`FMTBITS-1:0]     OutFmt,             // output format
   input  logic [2:0]              Frm,                // rounding mode
   input  logic                    Ms,                 // normalized sign

src/fpu/divremsqrt/divremsqrtroundsign.sv

@@ -27,7 +27,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 
-module roundsign(
+module divremsqrtroundsign(
   input logic         Xs,     // x sign
   input logic         Ys,     // y sign
   input logic         Sqrt,   // sqrt oppertion? (when using divsqrt unit)

src/fpu/divremsqrt/divremsqrtspecialcase.sv

@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-module specialcase(
+module divremsqrtspecialcase(
   input  logic                Xs,         // X sign
   input  logic [`NF:0]        Xm, Ym, // input significand's
   input  logic                XNaN, YNaN, // are the inputs NaN
@@ -48,7 +48,7 @@ module specialcase(
   input  logic                DivOp,      // is it a divsqrt opperation
   input  logic                DivByZero,  // divide by zero flag
   // outputs
-  output logic [`FLEN-1:0]    PostProcRes,// final result
+  output logic [`FLEN-1:0]    PostProcRes // final result
 );
 
   logic [`FLEN-1:0]   XNaNRes;    // X is NaN result

src/fpu/divremsqrt/drsu.sv

@@ -48,7 +48,7 @@ module drsu(
   input  logic                IntDivE, W64E,
   input  logic [2:0]          Frm,
   input  logic [2:0]          OpCtrl,
-  input  logic [`FMTBits:0]   Fmt,
+  input  logic [`FMTBITS:0]   Fmt,
   input  logic [1:0]          PostProcSel,
   output logic                FDivBusyE, IFDivStartE, FDivDoneE,
   output logic [`FLEN-1:0]    FResM,
@@ -88,7 +88,7 @@ module drsu(
                     .FlushE, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3M,
                     .Funct3E, .IntDivE, .FIntDivResultM,
                     .FDivDoneE, .IFDivStartE);
-  divremsqrtpostprocess divremsqrtpostprocess(.Xs(XsE), .Ys(YsE), .Frm(Frm), .Fmt(Fmt), .OpCtrl,
+  divremsqrtpostprocess divremsqrtpostprocess(.Xs(XsE), .Ys(YsE), .Xm(XmE), .Ym(YmE), .Frm(Frm), .Fmt(Fmt), .OpCtrl,
     .XZero(XZeroE), .YZero(YZeroE), .XInf(XInfE), .YInf(YInfE), .XNaN(XNaNE), .YNaN(YNaNE), .XSNaN(XSNaNE), 
     .YSNaN(YSNaNE), .PostProcSel,.DivSticky(DivStickyM), .DivQe(QeM), .DivQm(QmM), .PostProcRes(FResM), .PostProcFlg(FlgM));
 endmodule