formatting

src/ieu/alu.sv

@@ -58,15 +58,18 @@ module alu #(parameter WIDTH=32) (
   logic [WIDTH-1:0] rotA;                                                                   // XLEN bit input source to shifter
   logic [1:0]       shASelect;                                                              // select signal for shifter source generation mux 
 
-  assign shASelect = {W64,SubArith};
 
+  // Extract control signals from ALUControl.
+  assign {W64, SubArith, ALUOp} = ALUControl;
+
+  // Pack control signals into shifter select
+  assign shASelect = {W64,SubArith};
 
   if (`ZBS_SUPPORTED) begin: zbsdec
     decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB);
     assign CondMaskB = (BSelect[0]) ? MaskB : B;
   end else assign CondMaskB = B;
 
-
   // Sign/Zero extend mux
   if (WIDTH == 64) begin // rv64 must handle word s/z extensions
     always_comb 
@@ -99,9 +102,6 @@ module alu #(parameter WIDTH=32) (
     assign Rotate = BSelect[2] & (ALUSelect == 3'b001); //NOTE: Do we want to move this logic into the Decode Stage?
   end else assign Rotate = 1'b0;
 
-  // Extract control signals from ALUControl.
-  assign {W64, SubArith, ALUOp} = ALUControl;
-
   // Addition
   assign CondInvB = SubArith ? ~CondMaskB : CondMaskB;
   assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};

src/ieu/bmu/bmuctrl.sv

@@ -69,7 +69,7 @@ module bmuctrl(
   // Main Instruction Decoder
   always_comb
     casez({OpD, Funct7D, Funct3D})
-    // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp
+    // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_IllegalBitmanipInstrD
       // ZBS
       17'b0010011_0100100_001:   BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0;  // bclri
       17'b0010011_0100101_001: if (`XLEN == 64)