From b62bacbac31cec5d9f4dee6ab9eb27c1a1f4b0b1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 16 Feb 2023 11:05:24 -0600 Subject: [PATCH 1/2] keep this commit off of cvw. --- src/generic/mem/ram1p1rwbe.sv | 2 +- src/generic/mem/ram1p1rwbe_64x128.sv | 3 +- src/generic/mem/ram1p1rwbe_64x44.sv | 9 ++- src/generic/mem/ram2p1r1wbe.sv | 105 ++++++++++++++++++++++++- src/generic/mem/ram2p1r1wbe_1024x68.sv | 4 +- src/generic/mem/ram2p1r1wbe_128x64.sv | 50 ++++++++++++ src/generic/mem/ram2p1r1wbe_512x64.sv | 50 ++++++++++++ src/generic/mem/ram2p1r1wbe_64x32.sv | 4 +- src/generic/mem/rom1p1r_128x64.sv | 3 +- 9 files changed, 218 insertions(+), 12 deletions(-) create mode 100644 src/generic/mem/ram2p1r1wbe_128x64.sv create mode 100644 src/generic/mem/ram2p1r1wbe_512x64.sv diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index e33e708a3..a77a0eee9 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -69,7 +69,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin + end else if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin genvar index; // 64 x 128-bit SRAM logic [WIDTH-1:0] BitWriteMask; diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index fa8e32f0b..095f77c0d 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -35,6 +35,7 @@ module ram1p1rwbe_64x128( ); // replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor - generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + ts1n28hpcpsvtb64x128m4sw sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); +// generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index 7fa71f312..77ba09510 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -29,12 +29,13 @@ module ram1p1rwbe_64x44( input logic CEB, input logic WEB, input logic [5:0] A, - input logic [127:0] D, - input logic [127:0] BWEB, - output logic [127:0] Q + input logic [43:0] D, + input logic [43:0] BWEB, + output logic [43:0] Q ); // replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor - generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + TS1N28HPCPSVTB64X44M4SW sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + //generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 08c232bba..0daac6ff8 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -45,8 +45,6 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( ); logic [WIDTH-1:0] mem[DEPTH-1:0]; - localparam SRAMWIDTH = 32; - localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; // *************************************************************************** // TRUE Smem macro @@ -64,7 +62,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); - end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin + end else if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -78,6 +76,9 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin + localparam SRAMWIDTH = 32; + localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; + logic [SRAMWIDTH-1:0] SRAMReadData; logic [SRAMWIDTH-1:0] SRAMWriteData; logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0]; @@ -106,6 +107,104 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(SRAMReadData), .QB()); + end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 4096) begin + + localparam SRAMWIDTH = 64; + localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; + + logic [SRAMWIDTH-1:0] SRAMReadData; + logic [SRAMWIDTH-1:0] SRAMWriteData; + logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0]; + logic [SRAMNUMSETS-1:0] SRAMBitMaskPre; + logic [SRAMWIDTH-1:0] SRAMBitMask; + logic [$clog2(DEPTH)-1:0] RA1Q; + + + onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre); + genvar index; + for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux + assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)]; + assign SRAMWriteData[index*2+1:index*2] = wd2; + assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}}; + end + flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q); + assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; + ram2p1r1wbe_128x64 memory2(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .DA('0), + .DB(SRAMWriteData), + .BWEBA('0), .BWEBB(SRAMBitMask), + .QA(SRAMReadData), + .QB()); + + end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 16384) begin + + localparam SRAMWIDTH = 64; + localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; + + logic [SRAMWIDTH-1:0] SRAMReadData; + logic [SRAMWIDTH-1:0] SRAMWriteData; + logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0]; + logic [SRAMNUMSETS-1:0] SRAMBitMaskPre; + logic [SRAMWIDTH-1:0] SRAMBitMask; + logic [$clog2(DEPTH)-1:0] RA1Q; + + + onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre); + genvar index; + for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux + assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)]; + assign SRAMWriteData[index*2+1:index*2] = wd2; + assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}}; + end + flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q); + assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; + ram2p1r1wbe_512x64 memory2(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .DA('0), + .DB(SRAMWriteData), + .BWEBA('0), .BWEBB(SRAMBitMask), + .QA(SRAMReadData), + .QB()); + + end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 65536) begin + + localparam SRAMWIDTH = 64; + localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; + + logic [SRAMWIDTH-1:0] SRAMReadData; + logic [SRAMWIDTH-1:0] SRAMWriteData; + logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0]; + logic [SRAMNUMSETS-1:0] SRAMBitMaskPre; + logic [SRAMWIDTH-1:0] SRAMBitMask; + logic [$clog2(DEPTH)-1:0] RA1Q; + + + onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre); + genvar index; + for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux + assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)]; + assign SRAMWriteData[index*2+1:index*2] = wd2; + assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}}; + end + flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q); + assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; + ram2p1r1wbe_2048x64 memory2(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .DA('0), + .DB(SRAMWriteData), + .BWEBA('0), .BWEBB(SRAMBitMask), + .QA(SRAMReadData), + .QB()); end else begin // *************************************************************************** diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index e6a6b6257..6dbc23b3c 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -42,7 +42,9 @@ module ram2p1r1wbe_1024x68( ); // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor - generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + TSDN28HPCPA1024X68M4MW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); +// generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, +// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_128x64.sv b/src/generic/mem/ram2p1r1wbe_128x64.sv new file mode 100644 index 000000000..49d2631ee --- /dev/null +++ b/src/generic/mem/ram2p1r1wbe_128x64.sv @@ -0,0 +1,50 @@ +/////////////////////////////////////////// +// ram2p1rwbe_128x64.sv +// +// Written: james.stine@okstate.edu 28 January 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram2p1r1wbe_128x64( + input logic CLKA, + input logic CLKB, + input logic CEBA, + input logic CEBB, + input logic WEBA, + input logic WEBB, + input logic [6:0] AA, + input logic [6:0] AB, + input logic [63:0] DA, + input logic [63:0] DB, + input logic [63:0] BWEBA, + input logic [63:0] BWEBB, + output logic [63:0] QA, + output logic [63:0] QB +); + + // replace "generic128x64RAM" with "TSDN..128X64.." module from your memory vendor + TSDN28HPCPA128X64M4FW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // generic128x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, +// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + +endmodule diff --git a/src/generic/mem/ram2p1r1wbe_512x64.sv b/src/generic/mem/ram2p1r1wbe_512x64.sv new file mode 100644 index 000000000..14fbea75c --- /dev/null +++ b/src/generic/mem/ram2p1r1wbe_512x64.sv @@ -0,0 +1,50 @@ +/////////////////////////////////////////// +// ram2p1rwbe_2048x64.sv +// +// Written: james.stine@okstate.edu 28 January 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram2p1r1wbe_2048x64( + input logic CLKA, + input logic CLKB, + input logic CEBA, + input logic CEBB, + input logic WEBA, + input logic WEBB, + input logic [8:0] AA, + input logic [8:0] AB, + input logic [63:0] DA, + input logic [63:0] DB, + input logic [63:0] BWEBA, + input logic [63:0] BWEBB, + output logic [63:0] QA, + output logic [63:0] QB +); + + // replace "generic2048x64RAM" with "TSDN..2048X64.." module from your memory vendor + TSDN28HPCPA2048X64MMFW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // generic2048x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, +// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + +endmodule diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index 8bc19637d..713aa84f5 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -42,7 +42,9 @@ module ram2p1r1wbe_64x32( ); // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor - generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + TSDN28HPCPA64X32M4MW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, +// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv index 14e83f5f5..3c7ea4842 100755 --- a/src/generic/mem/rom1p1r_128x64.sv +++ b/src/generic/mem/rom1p1r_128x64.sv @@ -32,6 +32,7 @@ module rom1p1r_128x64( ); // replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor - generic64x128ROM romIP (.CLK, .CEB, .A, .Q); +ts3n28hpcpa128x64m8m romIP (.CLK, .CEB, .A, .Q); +// generic64x128ROM romIP (.CLK, .CEB, .A, .Q); endmodule From dd4064ea564dea36d6fe7424c31cea20136947c8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 16 Feb 2023 11:06:53 -0600 Subject: [PATCH 2/2] dc shell setup. --- synthDC/.synopsys_dc.setup | 51 ++++++++++++++------------------------ 1 file changed, 18 insertions(+), 33 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 2fdc11c27..f058bd820 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -3,39 +3,30 @@ set CURRENT_DIR [exec pwd] set search_path [list "./" ] -set tech $::env(TECH) - -if { [info exists ::env(RISCV)] } { - set timing_lib $::env(RISCV)/cad/lib -} else { - set timing_lib ../addins -} - -if {$tech == "sky130"} { - set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib - lappend search_path $s8lib -} elseif {$tech == "sky90"} { - set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib - lappend search_path $s9lib -} elseif {$tech == "tsmc28"} { - set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a - lappend search_path $s10lib -} +set memory ../memory +set pdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/7-track/tcbn28hpcplusbwp7t30p140-set/ +set tsmc28nlib $pdk/tcbn28hpcplusbwp7t30p140_190a_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp7t30p140_180a +set iolib1p8 /import/yukari1/pdk/TSMC/28/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a/ +lappend search_path $tsmc28nlib +lappend search_path $iolib1p8 +lappend search_path $memory # Synthetic libraries set synthetic_library [list dw_foundation.sldb] -# Set standard cell libraries +# Set OKSTATE standard cell libraries set target_library [list] -#lappend target_library scc9gena_tt_1.2v_25C.db -if {$tech == "sky130"} { - lappend target_library $s8lib/sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db -} elseif {$tech == "sky90"} { - lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db -} elseif {$tech == "tsmc28"} { - lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db -} +lappend target_library $iolib1p8/tphn28hpcpgv18tt0p9v1p8v25c.db +lappend target_library $tsmc28nlib/tcbn28hpcplusbwp7t30p140tt0p9v25c.db +lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db +lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db +lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db +lappend target_library $memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db +lappend target_library $memory/tsdn28hpcpa64x32m4mw_130a/NLDM/tsdn28hpcpa64x32m4mw_tt0p9v25c.db +lappend target_library $memory/dbs/tsdn28hpcpa128x64m4fw_tt0p9v25c.db +lappend target_library $memory/dbs/tsdn28hpcpa512x64m4fw_tt0p9v25c.db +lappend target_library $memory/dbs/tsdn28hpcpa2048x64m4mw_tt0p9v25c.db # Set Link Library set link_library "$target_library $synthetic_library" @@ -48,12 +39,6 @@ set cache_read $cache_write lappend search_path ./scripts lappend search_path ./hdl lappend search_path ./mapped -if {$tech == "tsmc28"} { - set memory /home/jstine/WallyMem/rv64gc/ - lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db - lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db - lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db -} # Set up User Information set company "Oklahoma State University"