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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2021-10-25 15:36:21 -05:00
commit c963ea1a64
40 changed files with 891 additions and 838 deletions
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2
wally-pipelined/linux-testgen/linux-testvectors/tvCopier.py
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@ -57,6 +57,6 @@ pyTee('_____________________________________________________________________')
for tvFile in copyList: for tvFile in copyList:
pyTee('Copying '+tvFile+' from Tera') pyTee('Copying '+tvFile+' from Tera')
os.system('scp '+tera+':/courses/e190ax/buildroot_boot/'+tvFile+' ./') os.system('scp -r'+tera+':/courses/e190ax/buildroot_boot/'+tvFile+' ./')
pyTee('Done!') pyTee('Done!')
logFile.close() logFile.close()

1
wally-pipelined/linux-testgen/linux-testvectors/tvLinker.sh
View File

@ -5,4 +5,5 @@ ln -s /courses/e190ax/buildroot_boot/ram.txt ram.txt
ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump vmlinux.objdump ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump vmlinux.objdump
ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump.addr vmlinux.objdump.addr ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump.addr vmlinux.objdump.addr
ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump.lab vmlinux.objdump.lab ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump.lab vmlinux.objdump.lab
ln -s /courses/e190ax/buildroot_boot/checkpoint8500000 ./checkpoint8500000
echo "Done!" echo "Done!"

25
wally-pipelined/linux-testgen/testvector-generation/CreateTrace.sh
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@ -1,25 +0,0 @@
#!/bin/bash
# Oftentimes this script runs so long you'll go to sleep.
# But you don't want the script to die when your computer goes to sleep.
# So consider invoking this with nohup (i.e. "nohup ./logAllBuildroot.sh")
# You can run "tail -f nohup.out" to see what would've
# outputted to the terminal if you didn't use nohup
# use on tera.
customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
# use on other systems
#customQemu="qemu-system-riscv64"
imageDir="../buildroot-image-output"
intermedDir="../linux-testvectors/intermediate-outputs"
outDir="../linux-testvectors"
# - Logs info needed by buildroot testbench
read -p "Warning: running this script will overwrite the contents of $outDir/all.txt.
Would you like to proceed? (y/n) " -n 1 -r
echo
if [[ $REPLY =~ ^[Yy]$ ]]
then
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -rtc clock=vm -icount shift=1 -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parseNew.py | ./remove_dup.awk > $outDir/all.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog
fi

35
wally-pipelined/linux-testgen/testvector-generation/GenerateCheckpoint.sh
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@ -1,35 +0,0 @@
#!/bin/bash
# Oftentimes this script runs so long you'll go to sleep.
# But you don't want the script to die when your computer goes to sleep.
# So consider invoking this with nohup (i.e. "nohup ./logAllBuildroot.sh")
# You can run "tail -f nohup.out" to see what would've
# outputted to the terminal if you didn't use nohup
# use on tera.
customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
# use on other systems
#customQemu="qemu-system-riscv64"
instrs=50000000
imageDir="../buildroot-image-output"
outDir="../linux-testvectors/checkpoint$instrs"
intermedDir="$outDir/intermediate-outputs"
read -p "This scripts is going to create a checkpoint at $instrs instrs.
Is that what you wanted? (y/n) " -n 1 -r
echo
if [[ $REPLY =~ ^[Yy]$ ]]
then
mkdir -p $outDir
mkdir -p $intermedDir
# Simulate QEMU, parse QEMU trace, run GDB script which logs a bunch of data at the checkpoint
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -rtc clock=vm -icount shift=1 -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1240 -S 2>&1 1>&2 | ./parse_qemu.py | ./parseNew.py | ./remove_dup.awk > $intermedDir/rawTrace.txt) & riscv64-unknown-elf-gdb -x ./checkpoint.gdb -ex "createCheckpoint $instrs \"$intermedDir\""
# Post-Process GDB outputs
./parseState.py "$outDir"
./fix_mem.py "$intermedDir/ramGDB.txt" "$outDir/ram.txt"
else
echo "You can change the number of instructions by editing the \"instrs\" variable in this script."
echo "Have a nice day!"
fi

30
wally-pipelined/linux-testgen/testvector-generation/checkpoint.gdb Executable file → Normal file
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@ -1,4 +1,4 @@
define createCheckpoint define genCheckpoint
# GDB config # GDB config
set pagination off set pagination off
set logging overwrite on set logging overwrite on
@ -11,24 +11,32 @@ define createCheckpoint
# QEMU Config # QEMU Config
maintenance packet Qqemu.PhyMemMode:1 maintenance packet Qqemu.PhyMemMode:1
# Argument Parsing
set $statePath=$arg1
set $ramPath=$arg1
eval "set $statePath = \"%s/stateGDB.txt\"", $statePath
eval "set $ramPath = \"%s/ramGDB.txt\"", $ramPath
# Symbol file # Symbol file
file ../buildroot-image-output/vmlinux file ../buildroot-image-output/vmlinux
# Argument Parsing
set $tcpPort=$arg0
set $instrCount=$arg1
set $statePath=$arg2
set $ramPath=$arg3
set $checkPC=$arg4
set $checkPCoccurences=$arg5
eval "set $statePath = \"%s/stateGDB.txt\"", $statePath
eval "set $ramPath = \"%s/ramGDB.txt\"", $ramPath
# Step over reset vector into actual code # Step over reset vector into actual code
stepi 1000 stepi 100
# Set breakpoint for where to stop # Set breakpoint for where to stop
b do_idle b do_idle
# Proceed to checkpoint # Proceed to checkpoint
printf "GDB proceeding to checkpoint at %d instrs\n", $arg0 printf "GDB proceeding to checkpoint at %d instrs\n", $instrCount
stepi $arg0-1000 #stepi $instrCount-1000
b *$checkPC
ignore 2 $checkPCoccurences
c
printf "Reached checkpoint at %d instrs\n", $arg0 printf "Reached checkpoint at %d instrs\n", $instrCount
# Log all registers to a file # Log all registers to a file
printf "GDB storing state to %s\n", $statePath printf "GDB storing state to %s\n", $statePath

24
wally-pipelined/linux-testgen/testvector-generation/debug.gdb Executable file
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@ -0,0 +1,24 @@
define debug
# Arguments
set $tcpPort=$arg0
# GDB config
set pagination off
set logging overwrite on
set logging redirect on
set confirm off
# Connect to QEMU session
eval "target extended-remote :%d",$tcpPort
# Symbol Files
file ../buildroot-image-output/vmlinux
# Run until Linux login prompt
b do_idle
ignore 1 2
c
kill
q
end

20
wally-pipelined/linux-testgen/testvector-generation/debug.sh Executable file
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@ -0,0 +1,20 @@
#!/bin/bash
source genSettings.sh
tcpPort=1237
# Run without GDB
($customQemu \
-M virt \
-nographic \
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
-singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on)
# Run with GDB
#($customQemu \
#-M virt \
#-nographic -serial /dev/null \
#-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
#-singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on \
#-gdb tcp::$tcpPort -S) \
#& riscv64-unknown-elf-gdb -x debug.gdb -ex "debug $tcpPort"

40
wally-pipelined/linux-testgen/testvector-generation/debugBuildroot.sh
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@ -1,40 +0,0 @@
# Oftentimes this script runs so long you'll go to sleep.
# But you don't want the script to die when your computer goes to sleep.
# So consider invoking this with nohup (i.e. "nohup ./logAllBuildroot.sh")
# You can run "tail -f nohup.out" to see what would've
# outputted to the terminal if you didn't use nohup
customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
#customQemu="qemu-system-riscv64"
imageDir="../buildroot-image-output"
intermedDir="../linux-testvectors/intermediate-outputs"
outDir="../linux-testvectors"
# =========== Debug the Process ==========
# Uncomment this version for QEMU debugging of kernel
# - good for poking around VM if it boots up
# - good for running QEMU commands (press "Ctrl-A" then "c" to open QEMU command prompt)
#$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -rtc clock=vm -icount shift=1
# Uncomment this version for GDB debugging of kernel
# - attempts to load in symbols from "vmlinux"
# - good for looking at backtraces when Linux gets stuck for some reason
$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -rtc clock=vm -icount shift=1 -gdb tcp::1237 -S & riscv64-unknown-elf-gdb -x gdbinit_debug
# Uncomment this version to generate qemu_output.txt
# - Uses GDB script
# - Logs raw QEMU output to qemu_output.txt
#($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -rtc clock=vm -icount shift=1 -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug
# Uncomment this version for parse_qemu.py debugging
# - Uses qemu_output.txt
# - Makes qemu_in_gdb_format.txt
# - Splits qemu_in_gdb_format.txt into chunks of 100,000 instrs
#cat $intermedDir/qemu_output.txt | ./parse_qemu.py >$intermedDir/qemu_in_gdb_format.txt
#cd $intermedDir
#split -d -l 5000000 ./qemu_in_gdb_format.txt --verbose
#cd ../../testvector-generation
# Uncomment this version for parse_gdb_output.py debugging
# - Uses qemu_in_gdb_format.txt
# - Makes testvectors
#cat $intermedDir/qemu_in_gdb_format.txt | ./parse_gdb_output.py "$outDir"

2
wally-pipelined/linux-testgen/testvector-generation/deprecated-scripts/find_csr.sh
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@ -1,2 +0,0 @@
#grep '=>.*csr' $1 | rev | cut -d' ' -f1 | rev | tee >(cut -d',' -f1) | cut -d',' -f2 | grep -Ev 'a[0-7]|t[0-6]|zero|[0-8]' | sort | uniq | paste -s -d, -
grep 'csr' /mnt/scratch/riscv_decodepc_threads/riscv_decodepc.txt.disassembly | rev | cut -d' ' -f1 | rev | tee >(cut -d',' -f1 | sort -u) >(cut -d',' -f2 | sort -u) | (cut -d',' -f3 | sort -u) | sort -u | paste -s -d, -

28
wally-pipelined/linux-testgen/testvector-generation/deprecated-scripts/fix_csrs.py
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@ -1,28 +0,0 @@
#! /usr/bin/python3
import sys, fileinput
sys.stderr.write("reminder: fix_csrs.py is nothing but hardcoded hackery to combat QEMU's faulty printing")
csrs = ['fcsr','mcause','mcounteren','medeleg','mepc','mhartid','mideleg','mie','mip','misa','mscratch','mstatus','mtval','mtvec','pmpaddr0','pmpcfg0','satp','scause','scounteren','sepc','sie','sscratch','sstatus','stval','stvec']
# just for now, since these CSRs aren't yet ready to be checked in testbench-linux
list(map(csrs.remove, ['fcsr','mhartid','pmpcfg0','pmpaddr0','mip']))
output_path = sys.argv[1]+'/'
print(f'output dir: {output_path}')
count = 0
csr = ''
with open('{}parsedCSRs.txt'.format(output_path), 'w') as fixedCSRs:
with open('{}/intermediate-outputs/unfixedParsedCSRs.txt'.format(output_path), 'r') as rawCSRs:
for l in rawCSRs:
fixedCSRs.write(l)
count += 1
if '---' in l:
count = 0
if (count%2 == 1): # every other line is CSR name
csr = l
else:
if ('stval' in csr) and ('8020007e' in l):
print('Adding stvec vector')
fixedCSRs.write('stvec\n')
fixedCSRs.write('ffffffff800000b0\n')

15
wally-pipelined/linux-testgen/testvector-generation/deprecated-scripts/logAllBuildroot.sh
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@ -1,15 +0,0 @@
# Oftentimes this script runs so long you'll go to sleep.
# But you don't want the script to die when your computer goes to sleep.
# So consider invoking this with nohup (i.e. "nohup ./logAllBuildroot.sh")
# You can run "tail -f nohup.out" to see what would've
# outputted to the terminal if you didn't use nohup
customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
#customQemu="qemu-system-riscv64"
imageDir="../buildroot-image-output"
intermedDir="../linux-testvectors/intermediate-outputs"
outDir="../linux-testvectors"
# - Logs info needed by buildroot testbench
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parse_gdb_output.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
./fix_csrs.py "$outDir"

1
wally-pipelined/linux-testgen/testvector-generation/deprecated-scripts/parseAllBusybear.sh
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@ -1 +0,0 @@
./combineGDBs.py && cat gdbcombined.txt | ./parse_gdb_output.py "/courses/e190ax/busybear_boot_new/"

173
wally-pipelined/linux-testgen/testvector-generation/deprecated-scripts/parse_gdb_output.py
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@ -1,173 +0,0 @@
#! /usr/bin/python3
import sys, fileinput
sys.stderr.write("reminder: parse_gdb_output.py takes input from stdin\n")
csrs = ['fcsr','mcause','mcounteren','medeleg','mepc','mhartid','mideleg','mie','mip','misa','mscratch','mstatus','mtval','mtvec','pmpaddr0','pmpcfg0','satp','scause','scounteren','sepc','sie','sscratch','sstatus','stval','stvec']
# just for now, since these CSRs aren't yet ready to be checked in testbench-linux
list(map(csrs.remove, ['fcsr','mhartid','pmpcfg0','pmpaddr0','mip']))
#output_path = '/courses/e190ax/busybear_boot_new/'
#output_path = '/courses/e190ax/buildroot_boot/'
output_path = sys.argv[1]+'/'
print(f'output dir: {output_path}')
instrs = -1
try:
with open('{}parsedPC.txt'.format(output_path), 'w') as wPC:
with open('{}parsedRegs.txt'.format(output_path), 'w') as wReg:
with open('{}parsedMemRead.txt'.format(output_path), 'w') as wMem:
with open('{}parsedMemWrite.txt'.format(output_path), 'w') as wMemW:
with open('{}/intermediate-outputs/unfixedParsedCSRs.txt'.format(output_path), 'w') as wCSRs:
firstCSR = True
curCSRs = {}
lastRead = ''
currentRead = ''
readOffset = ''
lastReadLoc = ''
readType = ''
lastReadType = ''
readLoc = ''
lineOffset = -1
lastRegs = ''
curRegs = ''
storeReg = ''
storeOffset = ''
storeLoc = ''
storeAMO = ''
lastAMO = ''
lastStoreReg = ''
lastStoreLoc = ''
for l in fileinput.input('-'):
l = l.split("#")[0].rstrip()
if l.startswith('=>'):
# Begin new instruction
instrs += 1
storeAMO = ''
if instrs % 10000 == 0:
print(instrs,flush=True)
# Instr in human assembly
wPC.write('{} ***\n'.format(' '.join(l.split(':')[1].split()[0:2])))
if '\tld' in l or '\tlw' in l or '\tlh' in l or '\tlb' in l:
currentRead = l.split()[-1].split(',')[0]
if len(l.split()[-1].split(',')) < 2:
print(l)
readOffset = l.split()[-1].split(',')[1].split('(')[0]
readLoc = l.split()[-1].split(',')[1].split('(')[1][:-1]
readType = l.split()[-2]
if 'amo' in l:
currentRead = l.split()[-1].split(',')[0]
readOffset = "0"
readLoc = l.split()[-1].split('(')[1][:-1]
readType = l.split()[-2]
storeOffset = "0"
storeLoc = readLoc
storeReg = l.split()[-1].split(',')[1]
storeAMO = l.split()[-2]
if '\tlr' in l:
currentRead = l.split()[-1].split(',')[0]
readOffset = "0"
readLoc = l.split()[-1].split('(')[1][:-1]
readType = "0" # *** I don't see that readType or lastReadType are ever used; we can probably get rid of them
if '\tsc' in l:
storeOffset = "0"
storeLoc = l.split()[-1].split('(')[1][:-1]
storeReg = l.split()[-1].split(',')[1]
if '\tsd' in l or '\tsw' in l or '\tsh' in l or '\tsb' in l:
s = l.split('#')[0].split()[-1]
storeReg = s.split(',')[0]
if len(s.split(',')) < 2:
print(s)
print(l)
if len(s.split(',')[1].split('(')) < 1:
print(s)
print(l)
storeOffset = s.split(',')[1].split('(')[0]
storeLoc = s.split(',')[1].split('(')[1][:-1]
lineOffset = 0
elif lineOffset != -1:
lineOffset += 1
if lineOffset == 1:
# Instr in hex comes one line after the instruction
wPC.write('{}\n'.format(l.split()[-1][2:]))
# As well as instr address
wPC.write('{}\n'.format(l.split()[0][2:].strip(":")))
elif lineOffset <= (1+32):
# Next 32 lines are the Register File
if lastRead == l.split()[0]:
readData = int(l.split()[1][2:], 16)
#readData <<= (8 * (lastReadLoc % 8)) <-- this was used to make byte and half-word instructions match what the bus unit sees in RV64. However, it is no longer needed because the testvectors are now compared against what the hart sees (not what the bus unit sees).
wMem.write('{:x}\n'.format(readData))
if readLoc == l.split()[0]:
readLoc = l.split()[1][2:]
if storeReg == l.split()[0]:
storeReg = l.split()[1]
if storeLoc == l.split()[0]:
storeLoc = l.split()[1][2:]
if lineOffset > (1+1):
# Start logging x1 onwards (we don't care about x0)
curRegs += '{}\n'.format(l.split()[1][2:])
#elif "pc" in l:
# wPC.write('{}\n'.format(l.split()[1][2:]))
if any([csr == l.split()[0] for csr in csrs]):
if l.split()[0] in curCSRs:
if curCSRs[l.split()[0]] != l.split()[1]:
if firstCSR:
wCSRs.write('---\n')
firstCSR = False
wCSRs.write('{}\n{}\n'.format(l.split()[0], l.split()[1][2:]))
else:
wCSRs.write('{}\n{}\n'.format(l.split()[0], l.split()[1][2:]))
curCSRs[l.split()[0]] = l.split()[1]
if '-----' in l: # end of each cycle
if curRegs != lastRegs:
if lastRegs == '':
wReg.write(curRegs)
else:
for i in range(32):
if curRegs.split('\n')[i] != lastRegs.split('\n')[i]:
wReg.write('{}\n'.format(i+1))
wReg.write('{}\n'.format(curRegs.split('\n')[i]))
break
lastRegs = curRegs
if lastAMO != '':
if 'amoadd' in lastAMO:
lastStoreReg = hex(int(lastStoreReg[2:], 16) + readData)[2:]
elif 'amoand' in lastAMO:
lastStoreReg = hex(int(lastStoreReg[2:], 16) & readData)[2:]
elif 'amoor' in lastAMO:
lastStoreReg = hex(int(lastStoreReg[2:], 16) | readData)[2:]
elif 'amoswap' in lastAMO:
lastStoreReg = hex(int(lastStoreReg[2:], 16))[2:]
else:
print(lastAMO)
exit()
#print('lastStoreReg {}\n'.format(lastStoreReg))
#print('lastStoreLoc '+str(lastStoreLoc))
wMemW.write('{}\n'.format(lastStoreReg))
wMemW.write('{:x}\n'.format(int(lastStoreLoc, 16)))
if storeReg != '' and storeOffset != '' and storeLoc != '' and storeAMO == '':
storeLocOffset = int(storeOffset,10) + int(storeLoc, 16)
#wMemW.write('{:x}\n'.format(int(storeReg, 16) << (8 * (storeLocOffset % 8))))
wMemW.write('{}\n'.format(storeReg[2:]))
wMemW.write('{:x}\n'.format(storeLocOffset))
if readOffset != '' and readLoc != '':
wMem.write('{:x}\n'.format(int(readOffset,10) + int(readLoc, 16)))
lastReadLoc = int(readOffset,10) + int(readLoc, 16)
lastReadType = readType
readOffset = ''
readLoc = ''
curRegs = ''
lineOffset = -1
lastRead = currentRead
currentRead = ''
lastStoreReg = storeReg
lastStoreLoc = storeLoc
storeReg = ''
storeOffset = ''
storeLoc = ''
lastAMO = storeAMO
except (FileNotFoundError):
print('please give gdb output file as argument')

7
wally-pipelined/linux-testgen/testvector-generation/deprecated-scripts/setup_OVP.sh
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@ -1,7 +0,0 @@
#!/bin/bash
source /cad/riscv/OVP/Imperas.20200630/bin/setup.sh
setupImperas /cad/riscv/OVP/Imperas.20200630 -m32
source /cad/riscv/OVP/Imperas.20200630/bin/switchRuntime.sh 2>/dev/null
echo 1 | switchRuntimeImperas
source /cad/riscv/OVP/Imperas.20200630/bin/switchISS.sh 2>/dev/null
echo 1 | switchISSImperas

2
wally-pipelined/linux-testgen/testvector-generation/deprecated-scripts/start_OVP.sh
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@ -1,2 +0,0 @@
#!/bin/bash
sh /cad/riscv/OVP/Imperas.20200630/Demo/Platforms/riscv_RV64GC_Virtio_Linux/harness/RUN_Virtio_Linux.sh --gdbconsole --gdbinit /mnt/scratch/riscv_testbench/gdbinit

15
wally-pipelined/linux-testgen/testvector-generation/gdbinit
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@ -1,15 +0,0 @@
set pagination off
set logging overwrite on
set logging redirect on
set logging file /mnt/scratch/riscv_testbench/riscv_boot_regs.txt
set logging on
x/i $pc
x/x $pc
info all-registers
while ($pc != 0xffffffe000018fa4)
si
x/i $pc
x/x $pc
info all-registers
end
set logging off

12
wally-pipelined/linux-testgen/testvector-generation/gdbinit_debug
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@ -1,12 +0,0 @@
set pagination off
file ../buildroot-image-output/fw_jump.elf
target extended-remote :1237
b *0x80200040
c
file ../buildroot-image-output/vmlinux
#b irqchip_plic_warm_init
#c
#b plic_init
#c
b do_idle
c

23
wally-pipelined/linux-testgen/testvector-generation/gdbinit_mem
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@ -1,23 +0,0 @@
set pagination off
target extended-remote :1235
set logging overwrite on
set logging redirect on
printf "Creating bootmemGDB.txt\n"
set logging file ../linux-testvectors/intermediate-outputs/bootmemGDB.txt
set logging on
x/4096xb 0x1000
set logging off
printf "Creating bootmem_untrimmed_GDB.txt\n"
printf "Warning - please verify that the second half of bootmem_untrimmed_GDB.txt is all 0s\n"
set logging file ../linux-testvectors/intermediate-outputs/bootmem_untrimmed_GDB.txt
set logging on
x/8192xb 0x1000
set logging off
printf "Creating ramGDB.txt\n"
set logging file ../linux-testvectors/intermediate-outputs/ramGDB.txt
set logging on
x/134217728xb 0x80000000
set logging off
set confirm off
kill
q

11
wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog
View File

@ -1,11 +0,0 @@
set pagination off
target extended-remote :1236
file ../buildroot-image-output/vmlinux
stepi 1000
b do_idle
ignore 1 2
c
# using 3 continues didn't work because the first breakpoint hit causes a pipe break error
set confirm off
kill
q

56
wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.gdb Executable file
View File

@ -0,0 +1,56 @@
define genCheckpoint
# GDB config
set pagination off
set logging overwrite on
set logging redirect on
set confirm off
# Argument Parsing
set $tcpPort=$arg0
set $instrCount=$arg1
set $statePath=$arg1
set $ramPath=$arg2
set $checkPC=$arg3
set $checkPCoccurences=$arg4
eval "set $statePath = \"%s/stateGDB.txt\"", $statePath
eval "set $ramPath = \"%s/ramGDB.txt\"", $ramPath
# Connect to QEMU session
eval "target extended-remote :%d",$tcpPort
# QEMU Config
maintenance packet Qqemu.PhyMemMode:1
# Symbol file
file ../buildroot-image-output/vmlinux
# Step over reset vector into actual code
stepi 100
# Set breakpoint for where to stop
b do_idle
# Proceed to checkpoint
printf "GDB proceeding to checkpoint at %d instrs\n", $instrCount
#stepi $instrCount-1000
b *$checkPC
ignore 2 $checkPCoccurences
c
printf "Reached checkpoint at %d instrs\n", $instrCount
# Log all registers to a file
printf "GDB storing state to %s\n", $statePath
eval "set logging file %s", $statePath
set logging on
info all-registers
set logging off
# Log main memory to a file
printf "GDB storing RAM to %s\n", $ramPath
eval "set logging file %s", $ramPath
set logging on
x/134217728xb 0x80000000
set logging off
kill
q
end

39
wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh Executable file
View File

@ -0,0 +1,39 @@
#!/bin/bash
source genSettings.sh
tcpPort=1236
instrs=50000000
checkOutDir="$outDir/checkpoint$instrs"
checkIntermedDir="$checkOutDir/intermediate-outputs"
read -p "This scripts is going to create a checkpoint at $instrs instrs.
Is that what you wanted? (y/n) " -n 1 -r
echo
if [[ $REPLY =~ ^[Yy]$ ]]
then
mkdir -p $checkOutDir
mkdir -p $checkIntermedDir
instr=$(sed "${instrs}q;d" "../linux-testvectors/all.txt")
echo "Found ${instrs}th instr: ${instr}."
pc=$(echo $instr | cut -d " " -f1)
asm=$(echo $instr | cut -d " " -f2)
occurences=$(($(head -$instrs "../linux-testvectors/all.txt" | grep -c "${pc} ${asm}")-1))
echo "It occurs ${occurences} times before the ${instrs}th instr."
# Simulate QEMU, parse QEMU trace, run GDB script which logs a bunch of data at the checkpoint
($customQemu \
-M virt \
-nographic \
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
-singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on,rr=replay,rrfile="$intermedDir/$recordFile" \
-gdb tcp::$tcpPort -S) \
& riscv64-unknown-elf-gdb -quiet -x genCheckpoint.gdb -ex "genCheckpoint $tcpPort $instrs \"$checkIntermedDir\" 0x$pc $occurences"
# Post-Process GDB outputs
./parseState.py "$checkOutDir"
./fix_mem.py "$checkIntermedDir/ramGDB.txt" "$checkOutDir/ram.txt"
tail -n+$instrs "$outDir/$traceFile" > "$checkOutDir/$traceFile"
else
echo "You can change the number of instructions by editing the \"instrs\" variable in this script."
echo "Have a nice day!"
fi

44
wally-pipelined/linux-testgen/testvector-generation/genInitMem.gdb Executable file
View File

@ -0,0 +1,44 @@
define genInitMem
# GDB config
set pagination off
set logging overwrite on
set logging redirect on
set confirm off
# Argument Parsing
set $tcpPort=$arg0
set $bootmemPath=$arg1
set $untrimmedBootmemPath=$arg1
set $ramPath=$arg1
eval "set $bootmemPath = \"%s/bootmemGDB.txt\"", $bootmemPath
eval "set $untrimmedBootmemPath = \"%s/untrimmedBootmemGDB.txt\"", $untrimmedBootmemPath
eval "set $ramPath = \"%s/ramGDB.txt\"", $ramPath
# Connect to QEMU session
eval "target extended-remote :%d",$tcpPort
# QEMU Config
maintenance packet Qqemu.PhyMemMode:1
printf "Creating %s\n",$bootmemPath
eval "set logging file %s", $bootmemPath
set logging on
x/4096xb 0x1000
set logging off
printf "Creating %s\n",$untrimmedBootmemPath
printf "Warning - please verify that the second half of %s is all 0s\n",$untrimmedBootmemPath
eval "set logging file %s", $untrimmedBootmemPath
set logging on
x/8192xb 0x1000
set logging off
printf "Creating %s\n", $ramPath
eval "set logging file %s", $ramPath
set logging on
x/134217728xb 0x80000000
set logging off
kill
q
end

27
wally-pipelined/linux-testgen/testvector-generation/genInitMem.sh Executable file
View File

@ -0,0 +1,27 @@
#!/bin/bash
source genSettings.sh
tcpPort=1235
read -p "Warning: running this script will overwrite the contents of memory dumps needed for simulation.
Would you like to proceed? (y/n) " -n 1 -r
echo
if [[ $REPLY =~ ^[Yy]$ ]]
then
($customQemu \
-M virt \
-nographic \
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
-gdb tcp::$tcpPort -S 2>/dev/null >/dev/null) \
& riscv64-unknown-elf-gdb -quiet -x genInitMem.gdb -ex "genInitMem $tcpPort \"$intermedDir\""
echo "Translating Mem from GDB to Questa format"
./fix_mem.py "$intermedDir/bootmemGDB.txt" "$outDir/bootmem.txt"
./fix_mem.py "$intermedDir/ramGDB.txt" "$outDir/ram.txt"
echo "Done"
echo "Creating debugging objdump of linux image"
riscv64-unknown-elf-objdump -D $imageDir/vmlinux > $outDir/vmlinux.objdump
extractFunctionRadix.sh $outDir/vmlinux.objdump
echo "Done"
fi

11
wally-pipelined/linux-testgen/testvector-generation/genSettings.sh Executable file
View File

@ -0,0 +1,11 @@
#!/bin/bash
# Warning! This is Tera-specific absolute path
# *** on the long term we'll want to include QEMU in the addins folder
export customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
export imageDir="../buildroot-image-output"
export outDir="../linux-testvectors-experimental"
export intermedDir="$outDir/intermediate-outputs"
export traceFile="all.txt"
export recordFile="all.qemu"
export tcpPort=1234

24
wally-pipelined/linux-testgen/testvector-generation/genTrace.gdb Executable file
View File

@ -0,0 +1,24 @@
define genTrace
# Arguments
set $tcpPort=$arg0
# GDB config
set pagination off
set logging overwrite on
set logging redirect on
set confirm off
# Connect to QEMU session
eval "target extended-remote :%d",$tcpPort
# Symbol Files
file ../buildroot-image-output/vmlinux
# Run until Linux login prompt
b do_idle
ignore 1 2
c
kill
q
end

24
wally-pipelined/linux-testgen/testvector-generation/genTrace.sh Executable file
View File

@ -0,0 +1,24 @@
#!/bin/bash
source genSettings.sh
tcpPort=1234
read -p "Warning: running this script will overwrite the contents of:
$outDir/$traceFile
$outDir/$recordFile
Would you like to proceed? (y/n) " -n 1 -r
echo
if [[ $REPLY =~ ^[Yy]$ ]]
then
mkdir -p $outDir
mkdir -p $intermedDir
($customQemu \
-M virt \
-nographic -serial /dev/null \
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
-singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on,rr=record,rrfile="$intermedDir/$recordFile" \
-d nochain,cpu,in_asm \
-gdb tcp::$tcpPort -S \
2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py | ./remove_dup.awk > "$outDir/$traceFile") \
& riscv64-unknown-elf-gdb -quiet -x genTrace.gdb -ex "genTrace $tcpPort"
fi

28
wally-pipelined/linux-testgen/testvector-generation/logBuildrootMem.sh
View File

@ -1,28 +0,0 @@
#!/bin/bash
# use on tera.
customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
# use on other systems
#customQemu="qemu-system-riscv64"
imageDir="../buildroot-image-output"
testVecDir="../linux-testvectors"
read -p "Warning: running this script will overwrite the contents of memory dumps needed for simulation.
Would you like to proceed? (y/n) " -n 1 -r
echo
if [[ $REPLY =~ ^[Yy]$ ]]
then
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1235 -S 2>/dev/null >/dev/null) &
riscv64-unknown-elf-gdb -x gdbinit_mem
echo "Translating Mem from GDB to Questa format"
./fix_mem.py "$testVecDir/intermediate-outputs/bootmemGDB.txt" "$testVecDir/bootmem.txt"
./fix_mem.py "$testVecDir/intermediate-outputs/ramGDB.txt" "$testVecDir/ram.txt"
echo "Done"
echo "Creating debugging objdump of linux image"
riscv64-unknown-elf-objdump -D $imageDir/vmlinux > $testVecDir/vmlinux.objdump
extractFunctionRadix.sh $testVecDir/vmlinux.objdump
echo "Done"
fi

0
wally-pipelined/linux-testgen/testvector-generation/parseNew.py → wally-pipelined/linux-testgen/testvector-generation/parseGDBtoTrace.py
View File

1
wally-pipelined/linux-testgen/testvector-generation/parse_qemu.py → wally-pipelined/linux-testgen/testvector-generation/parseQemuToGDB.py
View File

@ -110,6 +110,7 @@ def parseRegs(l):
# Main Code # # Main Code #
############# #############
for l in fileinput.input(): for l in fileinput.input():
#sys.stderr.write(l)
if l.startswith('qemu-system-riscv64: QEMU: Terminated via GDBstub'): if l.startswith('qemu-system-riscv64: QEMU: Terminated via GDBstub'):
break break
elif l.startswith('IN:'): elif l.startswith('IN:'):

29
wally-pipelined/linux-testgen/testvector-generation/parseState.py
View File

@ -34,12 +34,14 @@ stateGDBpath = outDir+'intermediate-outputs/stateGDB.txt'
if not os.path.exists(stateGDBpath): if not os.path.exists(stateGDBpath):
sys.exit('Error input file '+stateGDBpath+'not found') sys.exit('Error input file '+stateGDBpath+'not found')
listCSRs = ['hpmcounter','pmpcfg','pmpaddr'] singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus']
singleCSRs = ['mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','mcounteren','sscratch','scause','sepc','stvec','sedeleg','sideleg','scounteren','satp','mstatus'] thirtyTwoBitCSRs = ['mcounteren','scounteren']
listCSRs = ['hpmcounter','pmpaddr']
pmpcfg = ['pmpcfg']
# Initialize List CSR files to empty # Initialize List CSR files to empty
# (because later we'll open them in append mode) # (because later we'll open them in append mode)
for csr in listCSRs: for csr in listCSRs+pmpcfg:
outFileName = 'checkpoint-'+csr.upper() outFileName = 'checkpoint-'+csr.upper()
outFile = open(outDir+outFileName, 'w') outFile = open(outDir+outFileName, 'w')
outFile.close() outFile.close()
@ -47,7 +49,7 @@ for csr in listCSRs:
# Initial State for Main Loop # Initial State for Main Loop
currState = 'regFile' currState = 'regFile'
regFileIndex = 0 regFileIndex = 0
outFileName = 'checkpoint-regfile.txt' outFileName = 'checkpoint-RF'
outFile = open(outDir+outFileName, 'w') outFile = open(outDir+outFileName, 'w')
# Main Loop # Main Loop
@ -60,7 +62,9 @@ with open(stateGDBpath, 'r') as stateGDB:
if (regFileIndex == 0 and name != 'zero'): if (regFileIndex == 0 and name != 'zero'):
print('Whoops! Expected regFile registers to come first, starting with zero') print('Whoops! Expected regFile registers to come first, starting with zero')
exit(1) exit(1)
outFile.write(val+'\n') if (name != 'zero'):
# Wally doesn't need to know zero=0
outFile.write(val+'\n')
regFileIndex += 1 regFileIndex += 1
if (regFileIndex == 32): if (regFileIndex == 32):
outFile.close() outFile.close()
@ -71,9 +75,24 @@ with open(stateGDBpath, 'r') as stateGDB:
outFile = open(outDir+outFileName, 'w') outFile = open(outDir+outFileName, 'w')
outFile.write(val+'\n') outFile.write(val+'\n')
outFile.close() outFile.close()
if name in thirtyTwoBitCSRs:
outFileName = 'checkpoint-'+name.upper()
outFile = open(outDir+outFileName, 'w')
val = int(val,16) & 0xffffffff
outFile.write(hex(val)[2:]+'\n')
outFile.close()
elif name.strip('0123456789') in listCSRs: elif name.strip('0123456789') in listCSRs:
outFileName = 'checkpoint-'+name.upper().strip('0123456789') outFileName = 'checkpoint-'+name.upper().strip('0123456789')
outFile = open(outDir+outFileName, 'a') outFile = open(outDir+outFileName, 'a')
outFile.write(val+'\n') outFile.write(val+'\n')
outFile.close() outFile.close()
elif name.strip('0123456789') in pmpcfg:
outFileName = 'checkpoint-'+name.upper().strip('0123456789')
outFile = open(outDir+outFileName, 'a')
fourPmp = int(val,16)
for i in range(3,-1,-1):
byte = (fourPmp >> 4*i) & 0xf
outFile.write(hex(byte)[2:]+'\n')
outFile.close()
print("Finished parsing state!") print("Finished parsing state!")

549
wally-pipelined/regression/linux-wave.do
View File

@ -2,55 +2,78 @@ onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset
add wave -noupdate /testbench/reset_ext
add wave -noupdate -radix unsigned /testbench/InstrCountW add wave -noupdate -radix unsigned /testbench/InstrCountW
add wave -noupdate /testbench/dut/hart/SATP_REGW add wave -noupdate /testbench/dut/hart/SATP_REGW
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
add wave -noupdate -expand -group {WriteBack stage} /testbench/dut/hart/ieu/InstrValidW add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DivBusyE
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -group PCS /testbench/dut/hart/PCF
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE add wave -noupdate -group PCS /testbench/dut/hart/PCE
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM add wave -noupdate -group PCS /testbench/dut/hart/PCM
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW add wave -noupdate -group PCS /testbench/PCW
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/PCD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/InstrValidD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM
add wave -noupdate -group {Memory Stage} /testbench/InstrMName
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
add wave -noupdate -group {WriteBack stage} /testbench/PCW
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
@ -98,11 +121,6 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
@ -112,12 +130,6 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
@ -126,23 +138,22 @@ add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
add wave -noupdate -expand -group alu -divider internals add wave -noupdate -group alu -divider internals
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
@ -160,13 +171,6 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
add wave -noupdate -expand -group PCS /testbench/PCW
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
@ -178,37 +182,30 @@ add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
add wave -noupdate /testbench/dut/hart/mdu/genblk1/div/StartDivideE add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
add wave -noupdate /testbench/dut/hart/mdu/genblk1/div/BusyE add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
add wave -noupdate /testbench/dut/hart/mdu/genblk1/div/DivDoneM add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate /testbench/dut/hart/mdu/genblk1/div/DivInitE add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCNextIndexF add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits} add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits} add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits} add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits} add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
@ -230,171 +227,170 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW add wave -noupdate -group lsu -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
add wave -noupdate -expand -group lsu -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM add wave -noupdate -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag} add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall add wave -noupdate -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit add wave -noupdate -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
add wave -noupdate -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW add wave -noupdate -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
@ -491,7 +487,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPC
add wave -noupdate -group {debug trace} -expand -group mem /testbench/line add wave -noupdate -group {debug trace} -expand -group mem /testbench/line
add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM
add wave -noupdate -group {debug trace} -expand -group wb /testbench/dut/hart/ieu/c/InstrValidW
add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW
@ -515,7 +510,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {37454355 ns} 0} WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {229 ns} 0}
quietly wave cursor active 2 quietly wave cursor active 2
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 314 configure wave -valuecolwidth 314
@ -531,4 +526,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {37454022 ns} {37455158 ns} WaveRestoreZoom {182 ns} {330 ns}

4
wally-pipelined/regression/regression-wally.py
View File

@ -34,10 +34,10 @@ def getBuildrootTC(short):
INSTR_LIMIT = 100000 # multiple of 100000 INSTR_LIMIT = 100000 # multiple of 100000
MAX_EXPECTED = 3000000 MAX_EXPECTED = 3000000
if short: if short:
BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do "+str(INSTR_LIMIT)+"\n!" BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do "+str(INSTR_LIMIT)+" 1 0\n!"
BRgrepstr=str(INSTR_LIMIT)+" instructions" BRgrepstr=str(INSTR_LIMIT)+" instructions"
else: else:
BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do 0\n!" BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do 0 1 0\n!"
BRgrepstr=str(MAX_EXPECTED)+" instructions" BRgrepstr=str(MAX_EXPECTED)+" instructions"
return TestCase(name="buildroot",cmd=BRcmd,grepstr=BRgrepstr) return TestCase(name="buildroot",cmd=BRcmd,grepstr=BRgrepstr)

34
wally-pipelined/regression/sim-buildroot
View File

@ -1 +1,33 @@
vsim -do wally-buildroot.do #!/bin/bash
# Defaults
INSTR_LIMIT=0
INSTR_WAVEON=1
CHECKPOINT=0
# Arg Parsing
for i in "$@"; do
case $i in
--INSTR_LIMIT=*)
INSTR_LIMIT="${i#*=}"
shift # past argument=value
;;
--INSTR_WAVEON=*)
INSTR_WAVEON="${i#*=}"
shift # past argument=value
;;
--CHECKPOINT=*)
CHECKPOINT="${i#*=}"
shift # past argument=value
;;
*)
# unknown option
;;
esac
done
echo "INSTR_LIMIT = ${INSTR_LIMIT}"
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
echo "CHECKPOINT = ${CHECKPOINT}"
vsim -do wally-buildroot.do $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT

35
wally-pipelined/regression/sim-buildroot-batch
View File

@ -1,4 +1,35 @@
INSTR_LIMIT=${1:-0} #!/bin/bash
# Defaults
INSTR_LIMIT=0
INSTR_WAVEON=1
CHECKPOINT=0
# Arg Parsing
for i in "$@"; do
case $i in
--INSTR_LIMIT=*)
INSTR_LIMIT="${i#*=}"
shift # past argument=value
;;
--INSTR_WAVEON=*)
INSTR_WAVEON="${i#*=}"
shift # past argument=value
;;
--CHECKPOINT=*)
CHECKPOINT="${i#*=}"
shift # past argument=value
;;
*)
# unknown option
;;
esac
done
echo "INSTR_LIMIT = ${INSTR_LIMIT}"
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
echo "CHECKPOINT = ${CHECKPOINT}"
vsim -c <<! vsim -c <<!
do wally-buildroot-batch.do $INSTR_LIMIT do wally-buildroot-batch.do $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
! !

3
wally-pipelined/regression/wally-buildroot-batch.do
View File

@ -29,8 +29,7 @@ vlog -lint +incdir+../config/buildroot +incdir+../config/shared ../testbench/tes
# start and run simulation # start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt work.testbench -G INSTR_LIMIT=$1 -G INSTR_WAVEON=$2 -G CHECKPOINT=$3 -o workopt
vopt work.testbench -G INSTR_LIMIT=$1 -o workopt
vsim workopt -suppress 8852,12070 vsim workopt -suppress 8852,12070

5
wally-pipelined/regression/wally-buildroot.do
View File

@ -30,13 +30,14 @@ vlog -lint +incdir+../config/buildroot +incdir+../config/shared ../testbench/tes
# start and run simulation # start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals # remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt +acc work.testbench -o workopt vopt +acc work.testbench -G INSTR_LIMIT=$1 -G INSTR_WAVEON=$2 -G CHECKPOINT=$3 -o workopt
vsim workopt -suppress 8852,12070 vsim workopt -suppress 8852,12070
#-- Run the Simulation #-- Run the Simulation
run -all run -all
do ./wave-dos/linux-waves.do do linux-wave.do
add log -r /*
run -all run -all
exec ./slack-notifier/slack-notifier.py exec ./slack-notifier/slack-notifier.py

3
wally-pipelined/src/privileged/csr.sv
View File

@ -59,7 +59,8 @@ module csr #(parameter
output logic STATUS_MIE, STATUS_SIE, output logic STATUS_MIE, STATUS_SIE,
output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW, output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW,
output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
input logic [4:0] SetFflagsM, input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW, output logic [2:0] FRM_REGW,
// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,

3
wally-pipelined/src/privileged/csrc.sv
View File

@ -97,7 +97,8 @@ module csrc #(parameter
logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM; logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
logic WriteCYCLEM, WriteINSTRETM; logic WriteCYCLEM, WriteINSTRETM;
logic [4:0] CounterNumM; logic [4:0] CounterNumM;
logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTER_REGW, HPMCOUNTERH_REGW; logic [`XLEN-1:0] HPMCOUNTER_REGW [`COUNTERS-1:3];
logic [`XLEN-1:0] HPMCOUNTERH_REGW [`COUNTERS-1:3];
logic InstrValidNotFlushedM; logic InstrValidNotFlushedM;
assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW; assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;

4
wally-pipelined/src/privileged/csrsr.sv
View File

@ -51,7 +51,7 @@ module csrsr (
// Lower privilege status registers are a subset of the full status register // Lower privilege status registers are a subset of the full status register
// *** consider adding MBE, SBE, UBE fields later from 20210108 draft spec // *** consider adding MBE, SBE, UBE fields later from 20210108 draft spec
generate generate
if (`XLEN==64) begin// RV64 if (`XLEN==64) begin: csrsr64 // RV64
assign MSTATUS_REGW = {STATUS_SD, 27'b0, STATUS_SXL, STATUS_UXL, 9'b0, assign MSTATUS_REGW = {STATUS_SD, 27'b0, STATUS_SXL, STATUS_UXL, 9'b0,
STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0, STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
@ -67,7 +67,7 @@ module csrsr (
/* STATUS_XS, STATUS_FS, /*STATUS_MPP, 8'b0, */ /* STATUS_XS, STATUS_FS, /*STATUS_MPP, 8'b0, */
/*STATUS_SPP, STATUS_MPIE, 1'b0 2'b0, STATUS_SPIE,*/ STATUS_UPIE, /*STATUS_SPP, STATUS_MPIE, 1'b0 2'b0, STATUS_SPIE,*/ STATUS_UPIE,
/*STATUS_MIE, 1'b0*/ 3'b0, /*STATUS_SIE, */STATUS_UIE}; /*STATUS_MIE, 1'b0*/ 3'b0, /*STATUS_SIE, */STATUS_UIE};
end else begin// RV32 end else begin: csrsr32 // RV32
assign MSTATUS_REGW = {STATUS_SD, 8'b0, assign MSTATUS_REGW = {STATUS_SD, 8'b0,
STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0, STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,

340
wally-pipelined/testbench/testbench-linux.sv
View File

@ -37,17 +37,24 @@
// 5: print everything // 5: print everything
module testbench(); module testbench();
///////////////////////////////////////////////////////////////////////////////
parameter INSTR_LIMIT = 0; // # of instructions at which to stop /////////////////////////////////// CONFIG ////////////////////////////////////
parameter INSTR_WAVEON = (INSTR_LIMIT > 10000) ? INSTR_LIMIT-10000 : 1; // # of instructions at which to turn on waves in graphical sim ///////////////////////////////////////////////////////////////////////////////
// Recommend setting all of these in do script using -G option
string ProgramAddrMapFile, ProgramLabelMapFile; parameter INSTR_LIMIT = 0; // # of instructions at which to stop
parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim
parameter CHECKPOINT = 0;
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////// DUT ///////////////////////////////////// ////////////////////////////////// HARDWARE ///////////////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
logic clk, reset; logic clk, reset, reset_ext;
logic [`AHBW-1:0] readDataExpected; initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
always begin clk <= 1; # 5; clk <= 0; # 5; end
logic [`AHBW-1:0] HRDATAEXT;
logic HREADYEXT, HRESPEXT;
logic HCLK, HRESETn;
logic [31:0] HADDR; logic [31:0] HADDR;
logic [`AHBW-1:0] HWDATA; logic [`AHBW-1:0] HWDATA;
logic HWRITE; logic HWRITE;
@ -56,51 +63,48 @@ module testbench();
logic [3:0] HPROT; logic [3:0] HPROT;
logic [1:0] HTRANS; logic [1:0] HTRANS;
logic HMASTLOCK; logic HMASTLOCK;
logic HCLK, HRESETn;
logic [`AHBW-1:0] HRDATAEXT;
logic HREADYEXT, HRESPEXT;
logic [31:0] GPIOPinsIn; logic [31:0] GPIOPinsIn;
logic [31:0] GPIOPinsOut, GPIOPinsEn; logic [31:0] GPIOPinsOut, GPIOPinsEn;
logic UARTSin, UARTSout; logic UARTSin;
logic UARTSout;
assign GPIOPinsIn = 0; assign GPIOPinsIn = 0;
assign UARTSin = 1; assign UARTSin = 1;
wallypipelinedsoc dut(.clk, .reset_ext, .reset,
.HRDATAEXT, .HREADYEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR,
.HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
.GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
.UARTSin, .UARTSout);
wallypipelinedsoc dut(.*); // Write Back stage signals not needed by Wally itself
parameter nop = 'h13;
logic [`XLEN-1:0] PCW;
logic [31:0] InstrW;
logic InstrValidW;
logic [`XLEN-1:0] MemAdrW, WriteDataW;
logic TrapW;
`define FLUSHW dut.hart.FlushW
`define STALLW dut.hart.StallW
flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW);
flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW);
flopenrc #(`XLEN) MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.dp.MemAdrM, MemAdrW);
flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW);
flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
//////////////////////// Signals & Shared Macros /////////////////////////// //////////////////////// Signals & Macro DECLARATIONS /////////////////////////
//////////////////////// AKA stuff that comes first ///////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
// Sorry if these have gotten decontextualized.
// Verilog expects them to be defined before they are used.
// -------------------
// Signal Declarations
// -------------------
// Testbench Core // Testbench Core
integer warningCount = 0; integer warningCount = 0;
integer errorCount = 0; integer errorCount = 0;
integer MIPexpected; integer fault;
// P, Instr Checking string ProgramAddrMapFile, ProgramLabelMapFile;
integer data_file_all; // Checkpointing
string name; string checkpointDir;
logic [1:0] initPriv;
// Write Back stage signals needed for trace compare, but don't actually // Signals used to parse the trace file
// exist in CPU. integer data_file_all;
logic [`XLEN-1:0] MemAdrW, WriteDataW; string name;
logic [`XLEN-1:0] PCW;
logic [31:0] InstrW;
logic InstrValidW;
// Write Back trace signals
logic checkInstrW;
//integer RegAdr;
integer fault;
logic TrapW;
// Signals used to parse the trace file.
logic checkInstrM;
integer matchCount; integer matchCount;
string line; string line;
logic [`XLEN-1:0] ExpectedPCM; logic [`XLEN-1:0] ExpectedPCM;
@ -113,8 +117,9 @@ module testbench();
integer TokenIndex; integer TokenIndex;
integer MarkerIndex; integer MarkerIndex;
integer NumCSRM; integer NumCSRM;
// Memory stage expected values from trace // Memory stage expected values from trace
logic checkInstrM;
integer MIPexpected;
string RegWriteM; string RegWriteM;
integer ExpectedRegAdrM; integer ExpectedRegAdrM;
logic [`XLEN-1:0] ExpectedRegValueM; logic [`XLEN-1:0] ExpectedRegValueM;
@ -122,8 +127,9 @@ module testbench();
logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM; logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM;
string ExpectedCSRArrayM[10:0]; string ExpectedCSRArrayM[10:0];
logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0]; logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0];
logic [`AHBW-1:0] readDataExpected;
// Write back stage expected values from trace // Write back stage expected values from trace
logic checkInstrW;
logic [`XLEN-1:0] ExpectedPCW; logic [`XLEN-1:0] ExpectedPCW;
logic [31:0] ExpectedInstrW; logic [31:0] ExpectedInstrW;
string textW; string textW;
@ -142,50 +148,182 @@ module testbench();
integer NumCSRPostWIndex; integer NumCSRPostWIndex;
logic [`XLEN-1:0] InstrCountW; logic [`XLEN-1:0] InstrCountW;
integer RequestDelayedMIP; integer RequestDelayedMIP;
// Useful Aliases
// ------ `define RF dut.hart.ieu.dp.regf.rf
// Macros `define PC dut.hart.ifu.pcreg.q
// ------ `define CSR_BASE dut.hart.priv.csr.genblk1
`define HPMCOUNTER `CSR_BASE.counters.genblk1.HPMCOUNTER_REGW
`define CSRwarn(CSR) \ `define PMP_BASE `CSR_BASE.csrm.genblk4
`define PMPCFG genblk2.PMPCFGreg.q
`define PMPADDR PMPADDRreg.q
`define MEDELEG `CSR_BASE.csrm.genblk1.MEDELEGreg.q
`define MIDELEG `CSR_BASE.csrm.genblk1.MIDELEGreg.q
`define MIE `CSR_BASE.csri.MIE_REGW
`define MIP `CSR_BASE.csri.MIP_REGW
`define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q
`define SCAUSE `CSR_BASE.csrs.genblk1.SCAUSEreg.q
`define MEPC `CSR_BASE.csrm.MEPCreg.q
`define SEPC `CSR_BASE.csrs.genblk1.SEPCreg.q
`define MCOUNTEREN `CSR_BASE.csrm.genblk3.MCOUNTERENreg.q
`define SCOUNTEREN `CSR_BASE.csrs.genblk1.genblk3.SCOUNTERENreg.q
`define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q
`define SSCRATCH `CSR_BASE.csrs.genblk1.SSCRATCHreg.q
`define MTVEC `CSR_BASE.csrm.MTVECreg.q
`define STVEC `CSR_BASE.csrs.genblk1.STVECreg.q
`define SATP `CSR_BASE.csrs.genblk1.genblk2.SATPreg.q
`define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW
`define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT
`define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT
`define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT
`define STATUS_MXR `CSR_BASE.csrsr.STATUS_MXR_INT
`define STATUS_SUM `CSR_BASE.csrsr.STATUS_SUM_INT
`define STATUS_MPRV `CSR_BASE.csrsr.STATUS_MPRV_INT
`define STATUS_FS `CSR_BASE.csrsr.STATUS_FS_INT
`define STATUS_MPP `CSR_BASE.csrsr.STATUS_MPP
`define STATUS_SPP `CSR_BASE.csrsr.STATUS_SPP
`define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE
`define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE
`define STATUS_UPIE `CSR_BASE.csrsr.STATUS_UPIE
`define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE
`define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE
`define STATUS_UIE `CSR_BASE.csrsr.STATUS_UIE
`define CURR_PRIV dut.hart.priv.privmodereg.q
`define INSTRET dut.hart.priv.csr.genblk1.counters.genblk1.genblk2.INSTRETreg.q
// Common Macros
`define checkCSR(CSR) \
begin \ begin \
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
$display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, InstrCountW, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, InstrCountW, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
if(`DEBUG_TRACE >= 3) fault = 1; \ if(`DEBUG_TRACE >= 3) fault = 1; \
end \ end \
end end
`define checkEQ(NAME, VAL, EXPECTED) \ `define checkEQ(NAME, VAL, EXPECTED) \
if(VAL != EXPECTED) begin \ if(VAL != EXPECTED) begin \
$display("%tns, %d instrs: %s %x differs from expected %x", $time, InstrCountW, NAME, VAL, EXPECTED); \ $display("%tns, %d instrs: %s %x differs from expected %x", $time, InstrCountW, NAME, VAL, EXPECTED); \
if ((NAME == "PCW") || (`DEBUG_TRACE >= 2)) fault = 1; \ if ((NAME == "PCW") || (`DEBUG_TRACE >= 2)) fault = 1; \
end end
///////////////////////////////////////////////////////////////////////////////
/////////////////////////////// INITIALIZATION ////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Checkpoint initializations
`define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \
initial begin \
#1; \
if (CHECKPOINT!=0) $readmemh({checkpointDir,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \
end
`define INIT_CHECKPOINT_SIMPLE_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
`MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
initial begin \
if (CHECKPOINT!=0) begin \
force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \
while (reset!==1) #1; \
while (reset!==0) #1; \
#1; \
release `SIGNAL; \
end \
end
// For the annoying case where the pathname to the array elements includes
// a "genblk<i>" in the signal name
`define INIT_CHECKPOINT_GENBLK_ARRAY(SIGNAL_BASE,SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
`MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
for (i=ARRAY_MIN; i<ARRAY_MAX+1; i=i+1) begin \
initial begin \
if (CHECKPOINT!=0) begin \
force `SIGNAL_BASE[i].`SIGNAL = init``SIGNAL[i]; \
while (reset!==1) #1; \
while (reset!==0) #1; \
#1; \
release `SIGNAL_BASE[i].`SIGNAL; \
end \
end \
end
// Note that dimension usage is very intentional here.
// We are dancing around (un)packed type requirements.
`define INIT_CHECKPOINT_VAL(SIGNAL,DIM) \
`MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,0,0) \
initial begin \
if (CHECKPOINT!=0) begin \
force `SIGNAL = init``SIGNAL[0]; \
while (reset!==1) #1; \
while (reset!==0) #1; \
#1; \
release `SIGNAL; \
end \
end
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1);
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3);
generate
genvar i;
`INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPCFG, [7:0],`PMP_ENTRIES-1,0);
`INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPADDR, [`XLEN-1:0],`PMP_ENTRIES-1,0);
endgenerate
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MIE, [11:0]);
`INIT_CHECKPOINT_VAL(MIP, [11:0]);
`INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(SCAUSE, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MEPC, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(SEPC, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MCOUNTEREN, [31:0]);
`INIT_CHECKPOINT_VAL(SCOUNTEREN, [31:0]);
`INIT_CHECKPOINT_VAL(MSCRATCH, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(SSCRATCH, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MTVEC, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(STVEC, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]);
`MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
assign initPriv = (initPC[0][`XLEN-1]) ? 2'h2 : 2'h3; // *** a hacky way to detect initial privilege level
initial begin initial begin
data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
InstrCountW = '0;
force dut.hart.priv.SwIntM = 0; force dut.hart.priv.SwIntM = 0;
force dut.hart.priv.TimerIntM = 0; force dut.hart.priv.TimerIntM = 0;
force dut.hart.priv.ExtIntM = 0; force dut.hart.priv.ExtIntM = 0;
$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
if (CHECKPOINT==0) begin // normal
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
InstrCountW = '0;
end else begin // checkpoint
$sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT);
checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir};
$readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM);
data_file_all = $fopen({checkpointDir,"all.txt"}, "r");
InstrCountW = CHECKPOINT;
// manual checkpoint initializations that don't neatly fit into MACRO
force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17];
force {`STATUS_FS,`STATUS_MPP} = initMSTATUS[0][14:11];
force {`STATUS_SPP,`STATUS_MPIE} = initMSTATUS[0][8:7];
force {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE} = initMSTATUS[0][5:3];
force {`STATUS_SIE,`STATUS_UIE} = initMSTATUS[0][1:0];
force `INSTRET = CHECKPOINT;
force `CURR_PRIV = initPriv;
while (reset!==1) #1;
while (reset!==0) #1;
#1;
release {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV};
release {`STATUS_FS,`STATUS_MPP};
release {`STATUS_SPP,`STATUS_MPIE};
release {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE};
release {`STATUS_SIE,`STATUS_UIE};
release `INSTRET;
release `CURR_PRIV;
end
end end
///////////////////////////////////////////////////////////////////////////////
assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM; //////////////////////////////////// CORE /////////////////////////////////////
assign checkInstrW = InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction. ///////////////////////////////////////////////////////////////////////////////
// Additonal W stage registers
`define FLUSHW dut.hart.FlushW
`define STALLW dut.hart.StallW
flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW);
flopenrc #(`XLEN) MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.dp.MemAdrM, MemAdrW);
flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW);
flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW);
flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);
flopenrc #(5) controlregW(clk, reset, `FLUSHW, ~`STALLW,
{dut.hart.ieu.c.RegWriteM, dut.hart.ieu.c.ResultSrcM, dut.hart.ieu.c.InstrValidM},
{dut.hart.ieu.c.RegWriteW, dut.hart.ieu.c.ResultSrcW, InstrValidW});
// Because qemu does not match exactly to wally it is necessary to read the the // Because qemu does not match exactly to wally it is necessary to read the the
// trace in the memory stage and detect if anything in wally must be overwritten. // trace in the memory stage and detect if anything in wally must be overwritten.
// This includes mtimer, interrupts, and various bits in mstatus and xtval. // This includes mtimer, interrupts, and various bits in mstatus and xtval.
@ -194,6 +332,7 @@ module testbench();
// on the next falling edge the expected state is compared to the wally state. // on the next falling edge the expected state is compared to the wally state.
// step 0: read the expected state // step 0: read the expected state
assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
always @(negedge clk) begin always @(negedge clk) begin
// always check PC, instruction bits // always check PC, instruction bits
if (checkInstrM) begin if (checkInstrM) begin
@ -343,6 +482,7 @@ module testbench();
end end
// step2: make all checks in the write back stage. // step2: make all checks in the write back stage.
assign checkInstrW = InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
always @(negedge clk) begin always @(negedge clk) begin
if(RequestDelayedMIP) begin if(RequestDelayedMIP) begin
$display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueW[NumCSRM]); $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueW[NumCSRM]);
@ -362,7 +502,8 @@ module testbench();
fault = 0; fault = 0;
if (`DEBUG_TRACE >= 1) begin if (`DEBUG_TRACE >= 1) begin
`checkEQ("PCW",PCW,ExpectedPCW) `checkEQ("PCW",PCW,ExpectedPCW)
`checkEQ("InstrW",InstrW,ExpectedInstrW) //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
// compressed to uncompressed conversion
`checkEQ("Instr Count",dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW,InstrCountW) `checkEQ("Instr Count",dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW,InstrCountW)
#2; // delay 2 ns. #2; // delay 2 ns.
if(`DEBUG_TRACE >= 5) begin if(`DEBUG_TRACE >= 5) begin
@ -388,19 +529,19 @@ module testbench();
// check csr // check csr
for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin
case(ExpectedCSRArrayW[NumCSRPostWIndex]) case(ExpectedCSRArrayW[NumCSRPostWIndex])
"mhartid": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW) "mhartid": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW)
"mstatus": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW) "mstatus": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW)
"mtvec": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW) "mtvec": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW)
"mip": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIP_REGW) "mip": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MIP_REGW)
"mie": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIE_REGW) "mie": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MIE_REGW)
"mideleg":`CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW) "mideleg": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW)
"medeleg": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW) "medeleg": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW)
"mepc": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MEPC_REGW) "mepc": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MEPC_REGW)
"mtval": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW) "mtval": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW)
"sepc": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.SEPC_REGW) "sepc": `checkCSR(dut.hart.priv.csr.genblk1.csrs.SEPC_REGW)
"scause": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW) "scause": `checkCSR(dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW)
"stvec": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.STVEC_REGW) "stvec": `checkCSR(dut.hart.priv.csr.genblk1.csrs.STVEC_REGW)
"stval": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW) "stval": `checkCSR(dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW)
endcase endcase
end end
if (fault == 1) begin if (fault == 1) begin
@ -420,38 +561,10 @@ module testbench();
.ProgramLabelMapFile(ProgramLabelMapFile)); .ProgramLabelMapFile(ProgramLabelMapFile));
///////////////////////////////////////////////////////////////////////////////
//////////////////////////////// Testbench Core ///////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// --------------
// Initialization
// --------------
initial
begin
reset <= 1; # 22; reset <= 0;
end
// initial loading of memories
initial begin
$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
end
// -------
// Running
// -------
always
begin
clk <= 1; # 5; clk <= 0; # 5;
end
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Miscellaneous /////////////////////////////// //////////////////////////////// Extra Features ///////////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
// Instr Opcode Tracking // Instr Opcode Tracking
// For waveview convenience // For waveview convenience
@ -528,4 +641,3 @@ module testbench();
end end
endfunction endfunction
endmodule endmodule