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	busybear: add bootram section in the same manner as ram
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				@ -165,10 +165,11 @@ module testbench_busybear();
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  endgenerate
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					  endgenerate
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  logic [`XLEN-1:0] RAM[('h8000000 >> 3):0];
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					  logic [`XLEN-1:0] RAM[('h8000000 >> 3):0];
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					  logic [`XLEN-1:0] bootram[('h2000 >> 3):0];
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  logic [`XLEN-1:0] readRAM, readPC;
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					  logic [`XLEN-1:0] readRAM, readPC;
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  integer RAMAdr, RAMPC;
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					  integer RAMAdr, RAMPC;
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  assign RAMAdr = (HADDR - 'h80000000) >> 3;
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					  assign RAMAdr = (HADDR - (HADDR > 'h2fff ? 'h80000000 : 'h1000)) >> 3;
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  assign RAMPC = (PCF - 'h80000000) >> 3;
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					  assign RAMPC = (PCF - (PCF > 'h2fff ? 'h80000000 : 'h1000)) >> 3;
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  logic [63:0] readMask;
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					  logic [63:0] readMask;
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  assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0];
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					  assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0];
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  always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
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					  always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
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@ -185,6 +186,21 @@ module testbench_busybear();
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      readPC = RAM[RAMPC];
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					      readPC = RAM[RAMPC];
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    end
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					    end
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  end
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					  end
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					  // there's almost certianly a better way than just copying this, but its simple enough for now:
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					  always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
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					    if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h1000 && HADDR <= 'h2FFF)) begin
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					      if (HWRITE) begin
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					        bootram[RAMAdr] = (bootram[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask);
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					      end else begin
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					        readRAM = bootram[RAMAdr] & readMask;
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					      end
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					    end
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					  end
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					  always @(PCF) begin
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					    if (PCF >= 'h1000 && PCF <= 'h2FFF) begin
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					      readPC = bootram[RAMPC];
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					    end
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					  end
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  logic [`XLEN-1:0] readAdrExpected;
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					  logic [`XLEN-1:0] readAdrExpected;
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  // this might need to change
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					  // this might need to change
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