From 21a9ff248a2849d539adc3ead5e688f33e926bdf Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 16 Apr 2024 15:37:04 -0500 Subject: [PATCH 1/7] Fixed regression-wally so it actually produces covereage reports. --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index bdb58fea0..29471cb4f 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -208,7 +208,7 @@ def addTests(tests, sim): gs = test[3] else: gs = "All tests ran without failures" - cmdPrefix="wsim --sim " + sim + " " + config + cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config for t in suites: tc = TestCase( name=t, From dd3460c1a9f07394bfc2ef0906396f4df6ae4a78 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 16 Apr 2024 15:44:42 -0500 Subject: [PATCH 2/7] Fixed makefile and regression-wally so that code coverage now works. --- bin/regression-wally | 4 ++-- sim/Makefile | 42 +++++++++++++++++++++--------------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 29471cb4f..a73f937a5 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -381,7 +381,7 @@ def main(): # Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage. # Also it is slow to run. # configs.append(getBuildrootTC(boot=False)) - os.system('rm -f cov/*.ucdb') + os.system('rm -f questa/cov/*.ucdb') elif '--nightly' in sys.argv: TIMEOUT_DUR = 60*1440 # 1 day #configs.append(getBuildrootTC(boot=False)) @@ -407,7 +407,7 @@ def main(): # Coverage report if coverage: - os.system('make coverage') + os.system('make QuestaCoverage') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) diff --git a/sim/Makefile b/sim/Makefile index 0cae5053e..09d417124 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -17,28 +17,28 @@ all: riscoftests memfiles coveragetests deriv wally-riscv-arch-test: wallyriscoftests memfiles -coverage: cov/rv64gc_arch64i.ucdb +QuestaCoverage: questa/cov/rv64gc_arch64i.ucdb #iter-elf.bash --cover --search ../tests/coverage - vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log -# vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log - vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt - vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt - vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt - vcover report cov/cov.ucdb -details -instance=/core/ifu. > cov/rv64gc_coverage_ifu.rpt - vcover report cov/cov.ucdb -details -instance=/core/lsu. > cov/rv64gc_coverage_lsu.rpt - vcover report cov/cov.ucdb -details -instance=/core/fpu. > cov/rv64gc_coverage_fpu.rpt - vcover report cov/cov.ucdb -details -instance=/core/ieu. > cov/rv64gc_coverage_ieu.rpt - vcover report cov/cov.ucdb -below 100 -details -instance=/core/ebu. > cov/rv64gc_uncovered_ebu.rpt - vcover report cov/cov.ucdb -below 100 -details -instance=/core/priv. > cov/rv64gc_uncovered_priv.rpt - vcover report cov/cov.ucdb -below 100 -details -instance=/core/ifu. > cov/rv64gc_uncovered_ifu.rpt - vcover report cov/cov.ucdb -below 100 -details -instance=/core/lsu. > cov/rv64gc_uncovered_lsu.rpt - vcover report cov/cov.ucdb -below 100 -details -instance=/core/fpu. > cov/rv64gc_uncovered_fpu.rpt - vcover report cov/cov.ucdb -below 100 -details -instance=/core/ieu. > cov/rv64gc_uncovered_ieu.rpt - vcover report -hierarchical cov/cov.ucdb > cov/rv64gc_coverage_hierarchical.rpt - vcover report -below 100 -hierarchical cov/cov.ucdb > cov/rv64gc_uncovered_hierarchical.rpt -# vcover report -below 100 cov/cov.ucdb > cov/rv64gc_coverage.rpt -# vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt - vcover report -details -threshH 100 -html cov/cov.ucdb + vcover merge -out questa/cov/cov.ucdb questa/cov/rv64gc_arch64i.ucdb questa/cov/rv64gc*.ucdb -logfile questa/cov/log +# vcover merge -out questa/cov/cov.ucdb questa/cov/rv64gc_arch64i.ucdb questa/cov/rv64gc*.ucdb questa/cov/buildroot_buildroot.ucdb riscv.ucdb -logfile questa/cov/log + vcover report -details questa/cov/cov.ucdb > questa/cov/rv64gc_coverage_details.rpt + vcover report questa/cov/cov.ucdb -details -instance=/core/ebu. > questa/cov/rv64gc_coverage_ebu.rpt + vcover report questa/cov/cov.ucdb -details -instance=/core/priv. > questa/cov/rv64gc_coverage_priv.rpt + vcover report questa/cov/cov.ucdb -details -instance=/core/ifu. > questa/cov/rv64gc_coverage_ifu.rpt + vcover report questa/cov/cov.ucdb -details -instance=/core/lsu. > questa/cov/rv64gc_coverage_lsu.rpt + vcover report questa/cov/cov.ucdb -details -instance=/core/fpu. > questa/cov/rv64gc_coverage_fpu.rpt + vcover report questa/cov/cov.ucdb -details -instance=/core/ieu. > questa/cov/rv64gc_coverage_ieu.rpt + vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/ebu. > questa/cov/rv64gc_uncovered_ebu.rpt + vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/priv. > questa/cov/rv64gc_uncovered_priv.rpt + vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/ifu. > questa/cov/rv64gc_uncovered_ifu.rpt + vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/lsu. > questa/cov/rv64gc_uncovered_lsu.rpt + vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/fpu. > questa/cov/rv64gc_uncovered_fpu.rpt + vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/ieu. > questa/cov/rv64gc_uncovered_ieu.rpt + vcover report -hierarchical questa/cov/cov.ucdb > questa/cov/rv64gc_coverage_hierarchical.rpt + vcover report -below 100 -hierarchical questa/cov/cov.ucdb > questa/cov/rv64gc_uncovered_hierarchical.rpt +# vcover report -below 100 questa/cov/cov.ucdb > questa/cov/rv64gc_coverage.rpt +# vcover report -recursive questa/cov/cov.ucdb > questa/cov/rv64gc_recursive.rpt + vcover report -details -threshH 100 -html questa/cov/cov.ucdb allclean: clean all From 6f6b1fd1fd21dc74f80acac8fadd8705de8647d1 Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Tue, 16 Apr 2024 18:45:21 -0700 Subject: [PATCH 3/7] Add extra path to search for deriv/buildroot. --- sim/verilator/Makefile | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index 4042326a8..f4a9ff8a8 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -5,7 +5,7 @@ PARAMS?=-DVERILATOR=1 --no-trace-top NONPROF?=--stats WORKING_DIR=${WALLY}/sim/verilator TARGET=$(WORKING_DIR)/target -SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv +SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv WALLYCONF?=rv64gc TEST?=arch64i @@ -33,7 +33,7 @@ obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) -cc --binary \ $(OPT) $(PARAMS) $(NONPROF) \ --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ - "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \ + "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)" \ wrapper.c \ ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv @@ -44,8 +44,9 @@ obj_dir_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) -cc --binary \ --prof-cfuncs $(OPT) $(PARAMS) \ --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ + "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)" \ wrapper.c \ - "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv + ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv questa: time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)" From 392eedb342d247f95fa39dce70e6657ca1db34f9 Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Tue, 16 Apr 2024 18:54:11 -0700 Subject: [PATCH 4/7] Update sim/verilator/Makefile with constants for simplicity. --- sim/verilator/Makefile | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index f4a9ff8a8..28ec9b673 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -1,15 +1,20 @@ +SHELL := /bin/bash .PHONY: profile run questa clean +# verilator configurations OPT= PARAMS?=-DVERILATOR=1 --no-trace-top NONPROF?=--stats -WORKING_DIR=${WALLY}/sim/verilator -TARGET=$(WORKING_DIR)/target -SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv - WALLYCONF?=rv64gc TEST?=arch64i +# constants +WORKING_DIR=${WALLY}/sim/verilator +TARGET=$(WORKING_DIR)/target +DEPENDENCIES=${WALLY}/config/shared/*.vh ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv +INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)" +SOURCE_PATH=${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv + default: run profile: obj_dir_profiling/Vtestbench_$(WALLYCONF) @@ -26,27 +31,27 @@ run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF) time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files." -obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) +obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES) mkdir -p obj_dir_non_profiling time verilator \ --Mdir obj_dir_non_profiling -o Vtestbench_$(WALLYCONF) \ -cc --binary \ $(OPT) $(PARAMS) $(NONPROF) \ --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ - "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)" \ + $(INCLUDE_PATH) \ wrapper.c \ - ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv + $(SOURCE_PATH) -obj_dir_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) +obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES) mkdir -p obj_dir_profiling time verilator \ --Mdir obj_dir_profiling -o Vtestbench_$(WALLYCONF) \ -cc --binary \ --prof-cfuncs $(OPT) $(PARAMS) \ --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ - "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)" \ + $(INCLUDE_PATH) \ wrapper.c \ - ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv + $(SOURCE_PATH) questa: time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)" From 1b18568d870dac9d2b764adaf00861cca3561b3c Mon Sep 17 00:00:00 2001 From: Quswar Abid Date: Wed, 17 Apr 2024 09:39:21 -0700 Subject: [PATCH 5/7] the fix Rose provided in meeting --- testbench/testbench-imperas.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench-imperas.sv b/testbench/testbench-imperas.sv index 27bcdb73e..49f321d00 100644 --- a/testbench/testbench-imperas.sv +++ b/testbench/testbench-imperas.sv @@ -110,7 +110,7 @@ module testbench; $error("Must specify test directory using plusarg testDir"); end - if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.RAM); else $error("Imperas test bench requires BUS."); ProgramAddrMapFile = {testDir, "/ref/ref.elf.objdump.addr"}; From 91a88fa46c09f946da574e6362d1977dd1f200d7 Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Wed, 17 Apr 2024 09:52:54 -0700 Subject: [PATCH 6/7] Update sim/verilator/Makefile with more comments and merging variables. --- sim/verilator/Makefile | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index 28ec9b673..e212d1d13 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -9,11 +9,15 @@ WALLYCONF?=rv64gc TEST?=arch64i # constants +# assume WALLY variable is correctly configured in the shell environment WORKING_DIR=${WALLY}/sim/verilator TARGET=$(WORKING_DIR)/target -DEPENDENCIES=${WALLY}/config/shared/*.vh ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv +# INCLUDE_PATH are pathes that Verilator should search for files it needs INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)" -SOURCE_PATH=${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv +# SOURCES are source files +SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv +# DEPENDENCIES are configuration files and source files, which leads to recompilation of executables +DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES) default: run @@ -40,7 +44,7 @@ obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES) --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ $(INCLUDE_PATH) \ wrapper.c \ - $(SOURCE_PATH) + $(SOURCES) obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES) mkdir -p obj_dir_profiling @@ -51,7 +55,7 @@ obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES) --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ $(INCLUDE_PATH) \ wrapper.c \ - $(SOURCE_PATH) + $(SOURCES) questa: time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)" From 6f16b7e0c9e55122a4787bbcb70bbec266457515 Mon Sep 17 00:00:00 2001 From: Quswar Abid Date: Wed, 17 Apr 2024 10:25:36 -0700 Subject: [PATCH 7/7] updated the submodules -> riscv-arch-tests and riscv-dv --- addins/riscv-arch-test | 2 +- addins/riscv-dv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 8a0cdceca..59ae6e707 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b +Subproject commit 59ae6e7073ff40c7e1a1556547b2e8b2ba03ea04 diff --git a/addins/riscv-dv b/addins/riscv-dv index a7e27bc04..f0c570d11 160000 --- a/addins/riscv-dv +++ b/addins/riscv-dv @@ -1 +1 @@ -Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172 +Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580