diff --git a/config/shared/debug.vh b/config/shared/debug.vh index bee590f70..bb9d86bd1 100755 --- a/config/shared/debug.vh +++ b/config/shared/debug.vh @@ -155,7 +155,6 @@ `define FFLAGS_REGNO 16'h0001 `define FRM_REGNO 16'h0002 `define FCSR_REGNO 16'h0003 - // privileged/csrm `define MSTATUS_REGNO 16'h0300 `define MISA_REGNO 16'h0301 @@ -199,9 +198,46 @@ `define MIMPID_REGNO 16'h0F13 `define MHARTID_REGNO 16'h0F14 `define MCONFIGPTR_REGNO 16'h0F15 +// privileged/csr +`define SIP_REGNO 16'h0144 +`define MIP_REGNO 16'h0344 +// privileged/csrc +`define MHPMEVENTBASE_REGNO 16'h0320 +`define MHPMCOUNTERBASE_REGNO 16'h0B00 +`define MHPMCOUNTERHBASE_REGNO 16'h0B80 +`define HPMCOUNTERBASE_REGNO 16'h0C00 +`define TIME_REGNO 16'h0C01 + +`define HPMCOUNTERHBASE_REGNO 16'h0C80 +`define TIMEH_REGNO 16'h0C81 +// privileged/csrs +`define SSTATUS_REGNO 16'h0100 + +`define SIE_REGNO 16'h0104 +`define STVEC_REGNO 16'h0105 +`define SCOUNTEREN_REGNO 16'h0106 + +`define SENVCFG_REGNO 16'h010A + +`define SSCRATCH_REGNO 16'h0140 +`define SEPC_REGNO 16'h0141 +`define SCAUSE_REGNO 16'h0142 +`define STVAL_REGNO 16'h0143 +`define SIP_REGNO 16'h0144 + +`define STIMECMP_REGNO 16'h014D + +`define STIMECMPH_REGNO 16'h015D + +`define SATP_REGNO 16'h0180 +// privileged/csri +`define SIE_REGNO 16'h0104 +`define SIP_REGNO 16'h0144 +`define MIE_REGNO 16'h0304 +`define MIP_REGNO 16'h0344 // src/ieu/datapath `define X0_REGNO 16'h1000 diff --git a/src/debug/rad.sv b/src/debug/rad.sv index 9edc985ea..99801fda3 100644 --- a/src/debug/rad.sv +++ b/src/debug/rad.sv @@ -77,30 +77,42 @@ module rad import cvw::*; #(parameter cvw_t P) ( GPRegNo = 0; FPRegNo = 0; case (Regno) inside - [`USTATUS_REGNO:`UTVEC_REGNO], - [`USCRATCH_REGNO:`UIP_REGNO], - `SSTATUS_REGNO, - [`SEDELEG_REGNO:`SCOUNTEREN_REGNO], - [`SSCRATCH_REGNO:`SIP_REGNO], - `SATP_REGNO, + [`FFLAGS_REGNO:`FCSR_REGNO], [`MSTATUS_REGNO:`MCOUNTEREN_REGNO], - [`MHPMEVENT3_REGNO:`MIP_REGNO], - [`PMPCFG0_REGNO:`PMPCFG3_REGNO], - [`PMPADDR0_REGNO:`PMPADDR15_REGNO], + `MENVCFG_REGNO, + `MSTATUSH_REGNO, + `MENVCFGH_REGNO, + `MCOUNTINHIBIT_REGNO, + [`MSCRATCH_REGNO:`MIP_REGNO], + [`PMPCFG0_REGNO:`PMPADDRF_REGNO], // TODO This is variable len (P.PA_BITS)? [`TSELECT_REGNO:`TDATA3_REGNO], [`DCSR_REGNO:`DPC_REGNO], - `MCYCLE_REGNO, - [`MINSTRET_REGNO:`MHPMCOUNTER31_REGNO], - `MCYCLEH_REGNO, - [`MINSTRETH_REGNO:`MHPMCOUNTER31H_REGNO] : begin + `SIP_REGNO, + `MIP_REGNO, + `MHPMEVENTBASE_REGNO, + `MHPMCOUNTERBASE_REGNO, + `MHPMCOUNTERHBASE_REGNO, + [`HPMCOUNTERBASE_REGNO:`TIME_REGNO], + [`HPMCOUNTERHBASE_REGNO:`TIMEH_REGNO], + `SSTATUS_REGNO, + [`SIE_REGNO:`SCOUNTEREN_REGNO], + `SENVCFG_REGNO, + [`SSCRATCH_REGNO:`SIP_REGNO], + `STIMECMP_REGNO, + `STIMECMPH_REGNO, + `SATP_REGNO, + `SIE_REGNO, + `SIP_REGNO, + `MIE_REGNO, + `MIP_REGNO : begin ShiftCount = P.XLEN - 1; CSRegNo = 1; RegReadOnly = 1; // TODO: eventually DCSR (any maybe others) will be RW end - [`CYCLE_REGNO:`HPMCOUNTER31_REGNO], - [`CYCLEH_REGNO:`HPMCOUNTER31H_REGNO], - [`MVENDORID_REGNO:`MHARTID_REGNO] : begin + [`HPMCOUNTERBASE_REGNO:`TIME_REGNO], + [`HPMCOUNTERHBASE_REGNO:`TIMEH_REGNO], + [`MVENDORID_REGNO:`MCONFIGPTR_REGNO] : begin ShiftCount = P.XLEN - 1; CSRegNo = 1; RegReadOnly = 1; diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 40e785518..ece114c4e 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -64,7 +64,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] FIntDivResultW, // Result from integer division (to IEU) // Debug scan chain input logic DebugSel, - input logic [4:0] RegAddr, + input logic [4:0] DebugRegAddr, input logic DebugCapture, input logic DebugRegUpdate, input logic DebugScanEn, @@ -206,8 +206,8 @@ module fpu import cvw::*; #(parameter cvw_t P) ( .a4(WA1), .wd4(FResultWM), .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D)); assign FRegWriteWM = DebugSel ? DebugRegUpdate : FRegWriteW; - assign RA1 = DebugSel ? RegAddr : InstrD[19:15]; - assign WA1 = DebugSel ? RegAddr : RdW; + assign RA1 = DebugSel ? DebugRegAddr : InstrD[19:15]; + assign WA1 = DebugSel ? DebugRegAddr : RdW; assign FResultWM = DebugSel ? DebugFPRWriteD : FResultW; flopenrs #(P.FLEN) FPScanReg(.clk, .reset, .en(DebugCapture), .d(FRD1D), .q(DebugFPRWriteD), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanOut)); end else begin diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index d1e35257b..18892525b 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -82,7 +82,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( input logic GPRSel, input logic DebugCapture, input logic DebugRegUpdate, - input logic [4:0] RegAddr, + input logic [4:0] DebugRegAddr, input logic GPRScanIn, output logic GPRScanOut ); @@ -120,8 +120,8 @@ module datapath import cvw::*; #(parameter cvw_t P) ( if (P.DEBUG_SUPPORTED) begin regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteWM, Rs1DM, Rs2D, RdWM, ResultWM, R1D, R2D); assign RegWriteWM = GPRSel ? DebugRegUpdate : RegWriteW; - assign Rs1DM = GPRSel ? RegAddr : Rs1D; - assign RdWM = GPRSel ? RegAddr : RdW; + assign Rs1DM = GPRSel ? DebugRegAddr : Rs1D; + assign RdWM = GPRSel ? DebugRegAddr : RdW; assign ResultWM = GPRSel ? DebugGPRWriteD : ResultW; flopenrs #(P.XLEN) GPScanReg(.clk, .reset, .en(DebugCapture), .d(R1D), .q(DebugGPRWriteD), .scan(DebugScanEn & GPRSel), .scanin(GPRScanIn), .scanout(GPRScanOut)); end else begin diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index a36e08712..82f10c424 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -89,7 +89,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( output logic GPRScanOut, input logic DebugCapture, input logic DebugRegUpdate, - input logic [4:0] RegAddr + input logic [4:0] DebugRegAddr ); logic [2:0] ImmSrcD; // Select type of immediate extension @@ -142,5 +142,5 @@ module ieu import cvw::*; #(parameter cvw_t P) ( .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .DebugScanEn, .DebugScanIn(DSCR), .DebugScanOut, - .MiscSel, .GPRSel, .DebugCapture, .DebugRegUpdate, .RegAddr, .GPRScanIn, .GPRScanOut); + .MiscSel, .GPRSel, .DebugCapture, .DebugRegUpdate, .DebugRegAddr, .GPRScanIn, .GPRScanOut); endmodule