diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index 20500226a..b8c5c6bcd 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -94,7 +94,7 @@ module btb
     end else if ((UpdateEn) & ~StallM & ~FlushM) begin
       ValidBits[PCEIndex] <= #1 |InstrClassE;
     end
-	TablePredValidF = ValidBits[PCNextFIndex];
+	if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
   end
 
   assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;