diff --git a/wally-pipelined/regression/wave-dos/cache-waves.do b/wally-pipelined/regression/wave-dos/cache-waves.do
index 20c7061b3..c7b32e1ef 100644
--- a/wally-pipelined/regression/wave-dos/cache-waves.do
+++ b/wally-pipelined/regression/wave-dos/cache-waves.do
@@ -31,8 +31,11 @@ add wave -hex /testbench/dut/hart/ifu/ic/InstrPAdrF
 add wave -hex /testbench/dut/hart/ifu/ic/InstrAckF
 add wave -hex /testbench/dut/hart/ifu/ic/controller/ICacheMemWriteData
 add wave -hex /testbench/dut/hart/ifu/ic/controller/ICacheMemWritePAdr
+add wave -hex /testbench/dut/hart/ifu/ic/controller/MisalignedState
+add wave -hex /testbench/dut/hart/ifu/ic/controller/MisalignedHalfInstrF
 add wave -divider
 
+
 add wave -hex /testbench/dut/hart/ifu/PCE
 add wave -hex /testbench/dut/hart/ifu/InstrE
 add wave /testbench/InstrEName
diff --git a/wally-pipelined/src/ifu/icache.sv b/wally-pipelined/src/ifu/icache.sv
index 046126d39..0d9537606 100644
--- a/wally-pipelined/src/ifu/icache.sv
+++ b/wally-pipelined/src/ifu/icache.sv
@@ -233,7 +233,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
     // Machinery to request the correct addresses from main memory
     always_comb begin
         assign InstrReadF = FetchState & ~EndFetchState;
-        assign LineAlignedPCPF = {UpperPCPF, LowerPCF[11:OFFSETWIDTH], {OFFSETWIDTH{1'b0}}};
+        assign LineAlignedPCPF = {ICacheMemReadUpperPAdr, ICacheMemReadLowerAdr[11:OFFSETWIDTH], {OFFSETWIDTH{1'b0}}};
         assign InstrPAdrF = LineAlignedPCPF + FetchWordNum*(`XLEN/8);
         assign NextFetchWordNum = FetchState ? FetchWordNum+InstrAckF : {LOGWPL+1{1'b0}}; 
     end