diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index a669ce8db..2890b8b6a 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -85,8 +85,13 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
 add wave -noupdate /testbench/InstrFName
+add wave -noupdate -expand -group dcache /testbench/dut/hart/MemAdrM
+add wave -noupdate -expand -group dcache /testbench/dut/hart/MemPAdrM
+add wave -noupdate -expand -group dcache /testbench/dut/hart/WriteDataM
+add wave -noupdate -expand -group dcache /testbench/dut/hart/ReadDataM
+add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemRWM
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {332469 ns} 0} {{Cursor 3} {333566 ns} 0} {{Cursor 4} {675 ns} 0}
+WaveRestoreCursors {{Cursor 2} {363960 ns} 0} {{Cursor 3} {365915 ns} 0}
 quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 185
@@ -102,4 +107,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {333505 ns} {333689 ns}
+WaveRestoreZoom {365848 ns} {366032 ns}
diff --git a/wally-pipelined/src/ifu/RAsPredictor.sv b/wally-pipelined/src/ifu/RAsPredictor.sv
index d985209be..9090878de 100644
--- a/wally-pipelined/src/ifu/RAsPredictor.sv
+++ b/wally-pipelined/src/ifu/RAsPredictor.sv
@@ -44,6 +44,7 @@ module RASPredictor
 
   logic [StackSize-1:0]     PtrD, PtrQ, PtrP1, PtrM1;
   logic [StackSize-1:0] [`XLEN-1:0] memory;
+  integer 			    index;
   
   assign CounterEn = pop | push | incr;
 
@@ -60,8 +61,12 @@ module RASPredictor
 			   .d(PtrD),
 			   .q(PtrQ));
 
-  always_ff @ (posedge clk) begin
-    if(push) begin
+  // RAS must be reset. 
+  always_ff @ (posedge clk, posedge reset) begin
+    if(reset) begin
+      for(index=0; index<StackSize; index++)
+	memory[index] <= {`XLEN{1'b0}};
+    end else if(push) begin
       memory[PtrP1] <= #1 pushPC;
     end
   end
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index 36fbab684..c589035c7 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -67,7 +67,7 @@ module bpred
 
   // Part 1 decode the instruction class.
   // *** for now I'm skiping the compressed instructions
-  assign InstrClassF[3] = InstrF[5:0] == 7'h67 && InstrF[19:15] == 5'h01; // return
+  assign InstrClassF[3] = InstrF[6:0] == 7'h67 && InstrF[19:15] == 5'h01; // return
   // This is probably too much logic. 
   // *** This also encourages me to switch to predicting the class.
 
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 3753c3b14..2edeb9022 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -91,7 +91,7 @@ module wallypipelinedhart (
            
   ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
 
-  ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
+  ieu ieu(.*); // integer execution unit: integer register file, datapath and controller
   dmem dmem(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit
 
   ahblite ebu( // *** make IRData InstrF