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fix typo in csrd

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Matthew 2024-06-16 11:44:05 -05:00
parent d6256d1647
commit c853eeec9c
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src/privileged/csrd.sv
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@ -82,6 +82,7 @@ module csrd import cvw::*; #(parameter cvw_t P) (
end else if (EnterDebugMode) begin end else if (EnterDebugMode) begin
Prv <= PrivilegeModeW; Prv <= PrivilegeModeW;
Cause <= DebugCause; Cause <= DebugCause;
end
end end
flopenr #(4) DCSRreg (clk, reset, WriteDCSRM, flopenr #(4) DCSRreg (clk, reset, WriteDCSRM,