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I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.

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This commit is contained in:
Ross Thompson 2023-05-26 13:56:51 -05:00
parent b517a96261
commit c7e515634d
5 changed files with 75 additions and 73 deletions
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22
src/privileged/csrc.sv
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@ -30,17 +30,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module csrc import cvw::*; #(parameter cvw_t P,
MHPMCOUNTERBASE = 12'hB00,
MTIME = 12'hB01, // this is a memory-mapped register; no such CSR exists, and access should fault
MHPMCOUNTERHBASE = 12'hB80,
MTIMEH = 12'hB81, // this is a memory-mapped register; no such CSR exists, and access should fault
MHPMEVENTBASE = 12'h320,
HPMCOUNTERBASE = 12'hC00,
HPMCOUNTERHBASE = 12'hC80,
TIME = 12'hC01,
TIMEH = 12'hC81
) (
module csrc import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic StallE, StallM,
input logic FlushM,
@ -73,6 +63,16 @@ module csrc import cvw::*; #(parameter cvw_t P,
output logic IllegalCSRCAccessM
);
localparam MHPMCOUNTERBASE = 12'hB00;
localparam MTIME = 12'hB01; // this is a memory-mapped register; no such CSR exists, and access should faul;
localparam MHPMCOUNTERHBASE = 12'hB80;
localparam MTIMEH = 12'hB81; // this is a memory-mapped register; no such CSR exists, and access should fault
localparam MHPMEVENTBASE = 12'h320;
localparam HPMCOUNTERBASE = 12'hC00;
localparam HPMCOUNTERHBASE = 12'hC80;
localparam TIME = 12'hC01;
localparam TIMEH = 12'hC81;
logic [4:0] CounterNumM;
logic [P.XLEN-1:0] HPMCOUNTER_REGW[P.COUNTERS-1:0];
logic [P.XLEN-1:0] HPMCOUNTERH_REGW[P.COUNTERS-1:0];

11
src/privileged/csri.sv
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@ -27,11 +27,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module csri import cvw::*; #(parameter cvw_t P,
MIE = 12'h304,
MIP = 12'h344,
SIE = 12'h104,
SIP = 12'h144) (
module csri import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic CSRMWriteM, CSRSWriteM,
input logic [P.XLEN-1:0] CSRWriteValM,
@ -46,6 +42,11 @@ module csri import cvw::*; #(parameter cvw_t P,
logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
logic STIP;
localparam MIE = 12'h304;
localparam MIP = 12'h344;
localparam SIE = 12'h104;
localparam SIP = 12'h144;
// Interrupt Write Enables
assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP);
assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE);

78
src/privileged/csrm.sv
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@ -31,45 +31,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module csrm import cvw::*; #(parameter cvw_t P,
// Machine CSRs
MVENDORID = 12'hF11,
MARCHID = 12'hF12,
MIMPID = 12'hF13,
MHARTID = 12'hF14,
MCONFIGPTR = 12'hF15,
MSTATUS = 12'h300,
MISA_ADR = 12'h301,
MEDELEG = 12'h302,
MIDELEG = 12'h303,
MIE = 12'h304,
MTVEC = 12'h305,
MCOUNTEREN = 12'h306,
MSTATUSH = 12'h310,
MCOUNTINHIBIT = 12'h320,
MSCRATCH = 12'h340,
MEPC = 12'h341,
MCAUSE = 12'h342,
MTVAL = 12'h343,
MIP = 12'h344,
MTINST = 12'h34A,
PMPCFG0 = 12'h3A0,
// .. up to 15 more at consecutive addresses
PMPADDR0 = 12'h3B0,
// ... up to 63 more at consecutive addresses
TSELECT = 12'h7A0,
TDATA1 = 12'h7A1,
TDATA2 = 12'h7A2,
TDATA3 = 12'h7A3,
DCSR = 12'h7B0,
DPC = 12'h7B1,
DSCRATCH0 = 12'h7B2,
DSCRATCH1 = 12'h7B3,
// Constants
ZERO = {(P.XLEN){1'b0}},
MEDELEG_MASK = 16'hB3FF,
MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
) (
module csrm import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic UngatedCSRMWriteM, CSRMWriteM, MTrapM,
input logic [11:0] CSRAdrM,
@ -94,6 +56,44 @@ module csrm import cvw::*; #(parameter cvw_t P,
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
// Machine CSRs
localparam MVENDORID = 12'hF11;
localparam MARCHID = 12'hF12;
localparam MIMPID = 12'hF13;
localparam MHARTID = 12'hF14;
localparam MCONFIGPTR = 12'hF15;
localparam MSTATUS = 12'h300;
localparam MISA_ADR = 12'h301;
localparam MEDELEG = 12'h302;
localparam MIDELEG = 12'h303;
localparam MIE = 12'h304;
localparam MTVEC = 12'h305;
localparam MCOUNTEREN = 12'h306;
localparam MSTATUSH = 12'h310;
localparam MCOUNTINHIBIT = 12'h320;
localparam MSCRATCH = 12'h340;
localparam MEPC = 12'h341;
localparam MCAUSE = 12'h342;
localparam MTVAL = 12'h343;
localparam MIP = 12'h344;
localparam MTINST = 12'h34A;
localparam PMPCFG0 = 12'h3A0;
// .. up to 15 more at consecutive addresses
localparam PMPADDR0 = 12'h3B0;
// ... up to 63 more at consecutive addresses
localparam TSELECT = 12'h7A0;
localparam TDATA1 = 12'h7A1;
localparam TDATA2 = 12'h7A2;
localparam TDATA3 = 12'h7A3;
localparam DCSR = 12'h7B0;
localparam DPC = 12'h7B1;
localparam DSCRATCH0 = 12'h7B2;
localparam DSCRATCH1 = 12'h7B3;
// Constants
localparam ZERO = {(P.XLEN){1'b0}};
localparam MEDELEG_MASK = 16'hB3FF;
localparam MIDELEG_MASK = 12'h222; // we choose to not make machine interrupts delegable
// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
genvar i;
if (P.PMP_ENTRIES > 0) begin:pmp

28
src/privileged/csrs.sv
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@ -28,20 +28,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module csrs import cvw::*; #(parameter cvw_t P,
// Supervisor CSRs
SSTATUS = 12'h100,
SIE = 12'h104,
STVEC = 12'h105,
SCOUNTEREN = 12'h106,
SSCRATCH = 12'h140,
SEPC = 12'h141,
SCAUSE = 12'h142,
STVAL = 12'h143,
SIP= 12'h144,
STIMECMP = 12'h14D,
STIMECMPH = 12'h15D,
SATP = 12'h180) (
module csrs import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic CSRSWriteM, STrapM,
input logic [11:0] CSRAdrM,
@ -62,6 +49,19 @@ module csrs import cvw::*; #(parameter cvw_t P,
output logic STimerInt
);
// Supervisor CSRs
localparam SSTATUS = 12'h100;
localparam SIE = 12'h104;
localparam STVEC = 12'h105;
localparam SCOUNTEREN = 12'h106;
localparam SSCRATCH = 12'h140;
localparam SEPC = 12'h141;
localparam SCAUSE = 12'h142;
localparam STVAL = 12'h143;
localparam SIP= 12'h144;
localparam STIMECMP = 12'h14D;
localparam STIMECMPH = 12'h15D;
localparam SATP = 12'h180;
// Constants
localparam ZERO = {(P.XLEN){1'b0}};
localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9);

9
src/privileged/csru.sv
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@ -26,10 +26,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module csru import cvw::*; #(parameter cvw_t P,
FFLAGS = 12'h001,
FRM = 12'h002,
FCSR = 12'h003) (
module csru import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic InstrValidNotFlushedM,
input logic CSRUWriteM,
@ -43,6 +40,10 @@ module csru import cvw::*; #(parameter cvw_t P,
output logic IllegalCSRUAccessM
);
localparam FFLAGS = 12'h001;
localparam FRM = 12'h002;
localparam FCSR = 12'h003;
logic [4:0] FFLAGS_REGW;
logic [2:0] NextFRMM;
logic [4:0] NextFFLAGSM;