mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 10:15:19 +00:00
I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.
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@ -30,17 +30,7 @@
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// and limitations under the License.
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csrc import cvw::*; #(parameter cvw_t P,
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module csrc import cvw::*; #(parameter cvw_t P) (
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MHPMCOUNTERBASE = 12'hB00,
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MTIME = 12'hB01, // this is a memory-mapped register; no such CSR exists, and access should fault
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MHPMCOUNTERHBASE = 12'hB80,
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MTIMEH = 12'hB81, // this is a memory-mapped register; no such CSR exists, and access should fault
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MHPMEVENTBASE = 12'h320,
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HPMCOUNTERBASE = 12'hC00,
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HPMCOUNTERHBASE = 12'hC80,
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TIME = 12'hC01,
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TIMEH = 12'hC81
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) (
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input logic clk, reset,
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input logic clk, reset,
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input logic StallE, StallM,
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input logic StallE, StallM,
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input logic FlushM,
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input logic FlushM,
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@ -73,6 +63,16 @@ module csrc import cvw::*; #(parameter cvw_t P,
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output logic IllegalCSRCAccessM
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output logic IllegalCSRCAccessM
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);
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);
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localparam MHPMCOUNTERBASE = 12'hB00;
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localparam MTIME = 12'hB01; // this is a memory-mapped register; no such CSR exists, and access should faul;
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localparam MHPMCOUNTERHBASE = 12'hB80;
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localparam MTIMEH = 12'hB81; // this is a memory-mapped register; no such CSR exists, and access should fault
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localparam MHPMEVENTBASE = 12'h320;
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localparam HPMCOUNTERBASE = 12'hC00;
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localparam HPMCOUNTERHBASE = 12'hC80;
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localparam TIME = 12'hC01;
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localparam TIMEH = 12'hC81;
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logic [4:0] CounterNumM;
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logic [4:0] CounterNumM;
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logic [P.XLEN-1:0] HPMCOUNTER_REGW[P.COUNTERS-1:0];
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logic [P.XLEN-1:0] HPMCOUNTER_REGW[P.COUNTERS-1:0];
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logic [P.XLEN-1:0] HPMCOUNTERH_REGW[P.COUNTERS-1:0];
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logic [P.XLEN-1:0] HPMCOUNTERH_REGW[P.COUNTERS-1:0];
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@ -27,11 +27,7 @@
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// and limitations under the License.
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csri import cvw::*; #(parameter cvw_t P,
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module csri import cvw::*; #(parameter cvw_t P) (
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MIE = 12'h304,
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MIP = 12'h344,
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SIE = 12'h104,
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SIP = 12'h144) (
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input logic clk, reset,
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input logic clk, reset,
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input logic CSRMWriteM, CSRSWriteM,
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input logic CSRMWriteM, CSRSWriteM,
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input logic [P.XLEN-1:0] CSRWriteValM,
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input logic [P.XLEN-1:0] CSRWriteValM,
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@ -46,6 +42,11 @@ module csri import cvw::*; #(parameter cvw_t P,
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logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
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logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
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logic STIP;
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logic STIP;
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localparam MIE = 12'h304;
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localparam MIP = 12'h344;
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localparam SIE = 12'h104;
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localparam SIP = 12'h144;
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// Interrupt Write Enables
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// Interrupt Write Enables
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assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP);
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assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP);
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assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE);
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assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE);
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@ -31,45 +31,7 @@
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// and limitations under the License.
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csrm import cvw::*; #(parameter cvw_t P,
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module csrm import cvw::*; #(parameter cvw_t P) (
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// Machine CSRs
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MVENDORID = 12'hF11,
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MARCHID = 12'hF12,
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MIMPID = 12'hF13,
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MHARTID = 12'hF14,
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MCONFIGPTR = 12'hF15,
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MSTATUS = 12'h300,
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MISA_ADR = 12'h301,
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MEDELEG = 12'h302,
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MIDELEG = 12'h303,
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MIE = 12'h304,
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MTVEC = 12'h305,
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MCOUNTEREN = 12'h306,
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MSTATUSH = 12'h310,
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MCOUNTINHIBIT = 12'h320,
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MSCRATCH = 12'h340,
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MEPC = 12'h341,
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MCAUSE = 12'h342,
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MTVAL = 12'h343,
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MIP = 12'h344,
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MTINST = 12'h34A,
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PMPCFG0 = 12'h3A0,
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// .. up to 15 more at consecutive addresses
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PMPADDR0 = 12'h3B0,
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// ... up to 63 more at consecutive addresses
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TSELECT = 12'h7A0,
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TDATA1 = 12'h7A1,
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TDATA2 = 12'h7A2,
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TDATA3 = 12'h7A3,
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DCSR = 12'h7B0,
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DPC = 12'h7B1,
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DSCRATCH0 = 12'h7B2,
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DSCRATCH1 = 12'h7B3,
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// Constants
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ZERO = {(P.XLEN){1'b0}},
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MEDELEG_MASK = 16'hB3FF,
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MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
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) (
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input logic clk, reset,
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input logic clk, reset,
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input logic UngatedCSRMWriteM, CSRMWriteM, MTrapM,
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input logic UngatedCSRMWriteM, CSRMWriteM, MTrapM,
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input logic [11:0] CSRAdrM,
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input logic [11:0] CSRAdrM,
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@ -94,6 +56,44 @@ module csrm import cvw::*; #(parameter cvw_t P,
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logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
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logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
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logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
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logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
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// Machine CSRs
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localparam MVENDORID = 12'hF11;
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localparam MARCHID = 12'hF12;
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localparam MIMPID = 12'hF13;
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localparam MHARTID = 12'hF14;
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localparam MCONFIGPTR = 12'hF15;
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localparam MSTATUS = 12'h300;
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localparam MISA_ADR = 12'h301;
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localparam MEDELEG = 12'h302;
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localparam MIDELEG = 12'h303;
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localparam MIE = 12'h304;
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localparam MTVEC = 12'h305;
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localparam MCOUNTEREN = 12'h306;
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localparam MSTATUSH = 12'h310;
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localparam MCOUNTINHIBIT = 12'h320;
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localparam MSCRATCH = 12'h340;
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localparam MEPC = 12'h341;
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localparam MCAUSE = 12'h342;
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localparam MTVAL = 12'h343;
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localparam MIP = 12'h344;
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localparam MTINST = 12'h34A;
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localparam PMPCFG0 = 12'h3A0;
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// .. up to 15 more at consecutive addresses
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localparam PMPADDR0 = 12'h3B0;
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// ... up to 63 more at consecutive addresses
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localparam TSELECT = 12'h7A0;
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localparam TDATA1 = 12'h7A1;
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localparam TDATA2 = 12'h7A2;
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localparam TDATA3 = 12'h7A3;
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localparam DCSR = 12'h7B0;
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localparam DPC = 12'h7B1;
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localparam DSCRATCH0 = 12'h7B2;
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localparam DSCRATCH1 = 12'h7B3;
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// Constants
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localparam ZERO = {(P.XLEN){1'b0}};
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localparam MEDELEG_MASK = 16'hB3FF;
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localparam MIDELEG_MASK = 12'h222; // we choose to not make machine interrupts delegable
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// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
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// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
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genvar i;
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genvar i;
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if (P.PMP_ENTRIES > 0) begin:pmp
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if (P.PMP_ENTRIES > 0) begin:pmp
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@ -28,20 +28,7 @@
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// and limitations under the License.
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csrs import cvw::*; #(parameter cvw_t P,
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module csrs import cvw::*; #(parameter cvw_t P) (
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// Supervisor CSRs
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SSTATUS = 12'h100,
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SIE = 12'h104,
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STVEC = 12'h105,
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SCOUNTEREN = 12'h106,
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SSCRATCH = 12'h140,
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SEPC = 12'h141,
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SCAUSE = 12'h142,
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STVAL = 12'h143,
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SIP= 12'h144,
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STIMECMP = 12'h14D,
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STIMECMPH = 12'h15D,
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SATP = 12'h180) (
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input logic clk, reset,
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input logic clk, reset,
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input logic CSRSWriteM, STrapM,
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input logic CSRSWriteM, STrapM,
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input logic [11:0] CSRAdrM,
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input logic [11:0] CSRAdrM,
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@ -62,6 +49,19 @@ module csrs import cvw::*; #(parameter cvw_t P,
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output logic STimerInt
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output logic STimerInt
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);
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);
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// Supervisor CSRs
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localparam SSTATUS = 12'h100;
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localparam SIE = 12'h104;
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localparam STVEC = 12'h105;
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localparam SCOUNTEREN = 12'h106;
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localparam SSCRATCH = 12'h140;
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localparam SEPC = 12'h141;
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localparam SCAUSE = 12'h142;
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localparam STVAL = 12'h143;
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localparam SIP= 12'h144;
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localparam STIMECMP = 12'h14D;
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localparam STIMECMPH = 12'h15D;
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localparam SATP = 12'h180;
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// Constants
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// Constants
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localparam ZERO = {(P.XLEN){1'b0}};
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localparam ZERO = {(P.XLEN){1'b0}};
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localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9);
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localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9);
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@ -26,10 +26,7 @@
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// and limitations under the License.
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csru import cvw::*; #(parameter cvw_t P,
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module csru import cvw::*; #(parameter cvw_t P) (
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FFLAGS = 12'h001,
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FRM = 12'h002,
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FCSR = 12'h003) (
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input logic clk, reset,
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input logic clk, reset,
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input logic InstrValidNotFlushedM,
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input logic InstrValidNotFlushedM,
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input logic CSRUWriteM,
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input logic CSRUWriteM,
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@ -43,6 +40,10 @@ module csru import cvw::*; #(parameter cvw_t P,
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output logic IllegalCSRUAccessM
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output logic IllegalCSRUAccessM
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);
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);
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localparam FFLAGS = 12'h001;
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localparam FRM = 12'h002;
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localparam FCSR = 12'h003;
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logic [4:0] FFLAGS_REGW;
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logic [4:0] FFLAGS_REGW;
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logic [2:0] NextFRMM;
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logic [2:0] NextFRMM;
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logic [4:0] NextFFLAGSM;
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logic [4:0] NextFFLAGSM;
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