diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..69fb8f931
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,6 @@
+**/work
+
+#vsim work files to ignore
+transcript
+vsim.wlf
+wally-pipelined/wlft*
diff --git a/wally-pipelined/src/testbench-busybear.sv b/wally-pipelined/src/testbench-busybear.sv
new file mode 100644
index 000000000..405feaefa
--- /dev/null
+++ b/wally-pipelined/src/testbench-busybear.sv
@@ -0,0 +1,154 @@
+`include "wally-macros.sv"
+
+module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOUNTERS = 1)();
+
+  logic            clk, reset;
+  logic [XLEN-1:0] WriteDataM, DataAdrM;
+  logic [1:0]      MemRWM;
+  logic [31:0]     GPIOPinsIn;
+  logic [31:0]     GPIOPinsOut, GPIOPinsEn;
+
+  // instantiate device to be tested
+  logic [XLEN-1:0] PCF, ReadDataM;
+  logic [31:0] InstrF;
+  logic [7:0]  ByteMaskM;
+  logic        InstrAccessFaultF, DataAccessFaultM;
+  logic        TimerIntM, SwIntM; // from CLINT
+  logic        ExtIntM = 0; // not yet connected
+
+  // for now, seem to need these to be zero until we get a better idea
+  assign InstrAccessFaultF = 0;
+  assign DataAccessFaultM = 0;
+   
+  // instantiate processor and memories
+  wallypipelinedhart #(XLEN, MISA, ZCSR, ZCOUNTERS) dut(.ALUResultM(DataAdrM), .*);
+
+  // initialize test
+  initial
+    begin
+      reset <= 1; # 22; reset <= 0;
+    end
+  
+  // read pc trace file
+  integer data_file_PC, scan_file_PC;
+  initial begin
+    data_file_PC = $fopen("busybear-testgen/parsedPC.txt", "r");
+    if (data_file_PC == 0) begin
+      $display("file couldn't be opened");
+      $stop;
+    end 
+  end
+
+  // read register trace file
+  integer data_file_rf, scan_file_rf;
+  initial begin
+    data_file_rf = $fopen("busybear-testgen/parsedRegs.txt", "r");
+    if (data_file_rf == 0) begin
+      $display("file couldn't be opened");
+      $stop;
+    end 
+  end
+
+  // read memreads trace file
+  integer data_file_mem, scan_file_mem;
+  initial begin
+    data_file_mem = $fopen("busybear-testgen/parsedMemRead.txt", "r");
+    if (data_file_mem == 0) begin
+      $display("file couldn't be opened");
+      $stop;
+    end 
+  end
+
+  logic [63:0] rfExpected[31:1];
+  logic [63:0] pcExpected;
+  // I apologize for this hack, I don't have a clue how to properly work with packed arrays
+  logic [64*32:64] rf;
+  genvar i;
+  generate
+  for(i=1; i<32; i++) begin
+    assign rf[i*64+63:i*64] = dut.dp.regf.rf[i];
+  end
+  endgenerate
+
+  always @(rf) begin
+    for(int j=1; j<32; j++) begin
+      // read 31 integer registers
+      scan_file_rf = $fscanf(data_file_rf, "%x\n", rfExpected[j]);
+      // check things!
+      if (rf[j*64+63 -: 64] != rfExpected[j]) begin
+        $display("%t ps: rf[%0d] does not equal rf expected: %x, %x", $time, j, rf[j*64+63 -: 64], rfExpected[j]);
+    //    $stop;
+      end
+    end
+  end
+
+  // this might need to change
+  always @(MemRWM or DataAdrM) begin
+    if (MemRWM != 0) begin
+      scan_file_mem = $fscanf(data_file_mem, "%x\n", ReadDataM);
+    end
+  end
+
+  logic speculative, nextSpec;
+  initial begin
+    speculative = 0;
+    nextSpec = 0;
+  end
+
+  always @(PCF) begin
+    speculative <= nextSpec;
+    if (speculative) begin
+      speculative <= (PCF != pcExpected);
+    end
+    if (~speculative) begin
+      // first read instruction
+      scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF);
+      // then expected PC value
+      scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
+      // are we at a branch/jump?
+      case (InstrF[6:0]) //todo: add C versions of these
+        7'b1101111, //JAL
+        7'b1100111, //JALR
+        7'b1100011: //B
+          nextSpec <= 1;
+        default:
+          nextSpec <= 0;
+      endcase
+
+      //check things!
+      if ((~nextSpec) && (PCF !== pcExpected)) begin
+        $display("%t ps: PC does not equal PC expected: %x, %x", $time, PCF, pcExpected);
+      //  $stop;
+      end
+    end
+  end
+
+  // Track names of instructions
+  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+  logic [31:0] InstrW;
+  instrNameDecTB dec(InstrF, InstrFName);
+  instrTrackerTB #(XLEN) it(clk, reset, dut.dp.FlushE,
+                dut.dp.InstrDecompD, dut.dp.InstrE,
+                dut.dp.InstrM,  InstrW,
+                InstrDName, InstrEName, InstrMName, InstrWName);
+
+  // generate clock to sequence tests
+  always
+    begin
+      clk <= 1; # 5; clk <= 0; # 5;
+    end
+
+  //// check results
+  //always @(negedge clk)
+  //  begin
+  //    if(MemWrite) begin
+  //      if(DataAdr === 84 & WriteData === 71) begin
+  //        $display("Simulation succeeded");
+  //        $stop;
+  //      end else if (DataAdr !== 80) begin
+  //        $display("Simulation failed");
+  //        $stop;
+  //      end
+  //    end
+  //  end
+endmodule
diff --git a/wally-pipelined/wally-busybear.do b/wally-pipelined/wally-busybear.do
new file mode 100644
index 000000000..a52bda6a7
--- /dev/null
+++ b/wally-pipelined/wally-busybear.do
@@ -0,0 +1,126 @@
+# wally-pipelined.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with testbench_busybear 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# Use this wally-pipelined.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+vlog src/*.sv -suppress 2583
+
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+vopt +acc work.testbench_busybear -o workopt 
+vsim workopt
+
+view wave
+
+-- display input and output signals as hexidecimal values
+# Diplays All Signals recursively
+add wave /testbench_busybear/clk
+add wave /testbench_busybear/reset
+add wave -divider
+add wave -hex /testbench_busybear/pcExpected
+add wave -hex /testbench_busybear/dut/dp/PCF
+add wave -hex /testbench_busybear/dut/dp/InstrF
+add wave -divider
+# registers!
+add wave -hex /testbench_busybear/rfExpected
+add wave -hex /testbench_busybear/dut/dp/regf/rf[1]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[2]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[3]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[4]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[5]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[6]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[7]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[8]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[9]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[10]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[11]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[12]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[13]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[14]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[15]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[16]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[17]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[18]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[19]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[20]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[21]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[22]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[23]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[24]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[25]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[26]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[27]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[28]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[29]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[30]
+add wave -hex /testbench_busybear/dut/dp/regf/rf[31]
+add wave /testbench_busybear/InstrFName
+add wave -hex /testbench_busybear/dut/dp/PCD
+#add wave -hex /testbench_busybear/dut/dp/InstrD
+add wave /testbench_busybear/InstrDName
+#add wave -divider
+add wave -hex /testbench_busybear/dut/dp/PCE
+##add wave -hex /testbench_busybear/dut/dp/InstrE
+add wave /testbench_busybear/InstrEName
+#add wave -hex /testbench_busybear/dut/dp/SrcAE
+#add wave -hex /testbench_busybear/dut/dp/SrcBE
+#add wave -hex /testbench_busybear/dut/dp/ALUResultE
+#add wave /testbench_busybear/dut/dp/PCSrcE
+#add wave -divider
+add wave -hex /testbench_busybear/dut/dp/PCM
+##add wave -hex /testbench_busybear/dut/dp/InstrM
+add wave /testbench_busybear/InstrMName
+#add wave /testbench_busybear/dut/dmem/dtim/memwrite
+#add wave -hex /testbench_busybear/dut/dmem/AdrM
+#add wave -hex /testbench_busybear/dut/dmem/WriteDataM
+#add wave -divider
+add wave -hex /testbench_busybear/dut/dp/PCW
+##add wave -hex /testbench_busybear/dut/dp/InstrW
+add wave /testbench_busybear/InstrWName
+#add wave /testbench_busybear/dut/dp/RegWriteW
+#add wave -hex /testbench_busybear/dut/dp/ResultW
+#add wave -hex /testbench_busybear/dut/dp/RdW
+#add wave -divider
+##add ww
+#add wave -hex -r /testbench_busybear/*
+#
+#-- Set Wave Output Items 
+#TreeUpdate [SetDefaultTree]
+#WaveRestoreZoom {0 ps} {100 ps}
+#configure wave -namecolwidth 250
+#configure wave -valuecolwidth 120
+#configure wave -justifyvalue left
+#configure wave -signalnamewidth 0
+#configure wave -snapdistance 10
+#configure wave -datasetprefix 0
+#configure wave -rowmargin 4
+#configure wave -childrowmargin 2
+#set DefaultRadix hexadecimal
+#
+#-- Run the Simulation 
+run 300
+#run -all
+##quit