From c7c12cc3a8b3136176c36ba9b233c2b82d8c3a4d Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 6 Mar 2024 14:00:57 -0800 Subject: [PATCH] Fixed Lint issue on cacheLRU --- src/cache/cacheLRU.sv | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index cdd513547..865ebc74d 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -141,16 +141,17 @@ module cacheLRU // LRU storage must be reset for modelsim to run. However the reset value does not actually matter in practice. // This is a two port memory. // Every cycle must read from CacheSetData and each load/store must write the new LRU. + + // note: Verilator lint doesn't like <= for array initialization (https://verilator.org/warn/BLKLOOPINIT?v=5.021) + // Move to = to keep Verilator happy and simulator running fast always_ff @(posedge clk) begin if (reset | (InvalidateCache & ~FlushStage)) - for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= 0; // exclusion-tag: initialize - if(CacheEn) begin - if(LRUWriteEn) - LRUMemory[PAdr] <= NextLRU; - if(LRUWriteEn & (PAdr == CacheSetTag)) - CurrLRU <= #1 NextLRU; - else - CurrLRU <= #1 LRUMemory[CacheSetTag]; + for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = 0; // exclusion-tag: initialize + else if(CacheEn) begin + // Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value + if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = #1 NextLRU; + else CurrLRU = #1 LRUMemory[CacheSetTag]; + if(LRUWriteEn) LRUMemory[PAdr] = NextLRU; end end