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	renamed GrantData to LSUGrant
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				@ -84,7 +84,7 @@ module ahblite (
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  typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
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					  typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
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  statetype BusState, NextBusState;
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					  statetype BusState, NextBusState;
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  logic GrantData;
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					  logic LSUGrant;
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  logic [31:0] AccessAddress;
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					  logic [31:0] AccessAddress;
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  logic [2:0] ISize;
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					  logic [2:0] ISize;
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@ -132,12 +132,12 @@ module ahblite (
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  //  bus outputs
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					  //  bus outputs
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  assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
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					  assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
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  assign AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0];
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					  assign AccessAddress = (LSUGrant) ? LSUBusAdr[31:0] : IFUBusAdr[31:0];
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  assign HADDR = AccessAddress;
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					  assign HADDR = AccessAddress;
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  assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
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					  assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
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  assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize;
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					  assign HSIZE = (LSUGrant) ? {1'b0, LSUBusSize[1:0]} : ISize;
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  assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst.
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					  assign HBURST = (LSUGrant) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst.
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  /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE.
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					  /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE.
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        000: Single (SINGLE)
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					        000: Single (SINGLE)
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@ -153,7 +153,7 @@ module ahblite (
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  assign HPROT = 4'b0011; // not used; see Section 3.7
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					  assign HPROT = 4'b0011; // not used; see Section 3.7
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  assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
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					  assign HTRANS = (LSUGrant) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
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  assign HMASTLOCK = 0; // no locking supported
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					  assign HMASTLOCK = 0; // no locking supported
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  assign HWRITE = (NextBusState == MEMWRITE);
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					  assign HWRITE = (NextBusState == MEMWRITE);
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  // Byte mask for HWSTRB
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					  // Byte mask for HWSTRB
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