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busybear: better instrF checking

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So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
This commit is contained in:
Noah Boorstin 2021-03-08 19:48:12 +00:00
parent 1b206d5a3c
commit c780a25f92
2 changed files with 101 additions and 99 deletions
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190
wally-pipelined/regression/wally-busybear.do
View File

@ -1,37 +1,37 @@
# wally-pipelined.do # wally-pipelined.do
# #
# Modification by Oklahoma State University & Harvey Mudd College # Modification by Oklahoma State University & Harvey Mudd College
# Use with testbench_busybear # Use with testbench_busybear
# James Stine, 2008; David Harris 2021 # James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!! # Go Cowboys!!!!!!
# #
# Takes 1:10 to run RV64IC tests using gui # Takes 1:10 to run RV64IC tests using gui
# Use this wally-pipelined.do file to run this example. # Use this wally-pipelined.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt: # Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-pipelined.do # do wally-pipelined.do
# or, to run from a shell, type the following at the shell prompt: # or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-pipelined.do -c # vsim -do wally-pipelined.do -c
# (omit the "-c" to see the GUI while running from the shell) # (omit the "-c" to see the GUI while running from the shell)
onbreak {resume} onbreak {resume}
# create library # create library
if [file exists work-busybear] { if [file exists work-busybear] {
vdel -all -lib work-busybear vdel -all -lib work-busybear
} }
vlib work-busybear vlib work-busybear
# compile source files # compile source files
# suppress spurious warnngs about # suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time" # "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt # because vsim will run vopt
vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
# start and run simulation # start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals # remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt +acc work.testbench_busybear -o workopt vopt +acc work.testbench_busybear -o workopt
vsim workopt -suppress 8852,12070 vsim workopt -suppress 8852,12070
# load the branch predictors with known data. The value of the data is not important for function, but # load the branch predictors with known data. The value of the data is not important for function, but
@ -42,31 +42,33 @@ switch $argc {
1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory} 1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
} }
view wave view wave
-- display input and output signals as hexidecimal values -- display input and output signals as hexidecimal values
# Diplays All Signals recursively # Diplays All Signals recursively
add wave /testbench_busybear/clk add wave /testbench_busybear/clk
add wave /testbench_busybear/reset add wave /testbench_busybear/reset
add wave -divider add wave -divider
add wave -hex /testbench_busybear/PCtext add wave -hex /testbench_busybear/PCtext
add wave -hex /testbench_busybear/pcExpected add wave -hex /testbench_busybear/pcExpected
add wave -hex /testbench_busybear/dut/hart/ifu/PCF add wave -hex /testbench_busybear/dut/hart/ifu/PCF
add wave -hex /testbench_busybear/dut/hart/ifu/InstrF add wave -hex /testbench_busybear/dut/hart/ifu/InstrF
add wave -hex /testbench_busybear/dut/InstrF add wave -hex /testbench_busybear/dut/hart/ifu/StallD
add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
add wave /testbench_busybear/CheckInstrF add wave /testbench_busybear/CheckInstrF
add wave /testbench_busybear/lastCheckInstrF add wave /testbench_busybear/lastCheckInstrF
add wave /testbench_busybear/speculative add wave /testbench_busybear/speculative
add wave /testbench_busybear/lastPC2 add wave /testbench_busybear/lastPC2
add wave -divider add wave -divider
add wave -divider add wave -divider
add wave /testbench_busybear/dut/uncore/HSELBootTim add wave /testbench_busybear/dut/uncore/HSELBootTim
add wave /testbench_busybear/dut/uncore/HSELTim add wave /testbench_busybear/dut/uncore/HSELTim
add wave /testbench_busybear/dut/uncore/HREADTim add wave /testbench_busybear/dut/uncore/HREADTim
add wave /testbench_busybear/dut/uncore/dtim/HREADTim0 add wave /testbench_busybear/dut/uncore/dtim/HREADTim0
add wave /testbench_busybear/dut/uncore/HREADYTim add wave /testbench_busybear/dut/uncore/HREADYTim
add wave -divider add wave -divider
add wave /testbench_busybear/dut/uncore/HREADBootTim add wave /testbench_busybear/dut/uncore/HREADBootTim
add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0 add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0
add wave /testbench_busybear/dut/uncore/HREADYBootTim add wave /testbench_busybear/dut/uncore/HREADYBootTim
@ -80,8 +82,8 @@ add wave /testbench_busybear/dut/uncore/HRDATA
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG
add wave -divider add wave -divider
# registers! # registers!
add wave -hex /testbench_busybear/regExpected add wave -hex /testbench_busybear/regExpected
add wave -hex /testbench_busybear/regNumExpected add wave -hex /testbench_busybear/regNumExpected
add wave -hex /testbench_busybear/HWRITE add wave -hex /testbench_busybear/HWRITE
@ -121,49 +123,49 @@ add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[28]
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29]
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30]
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31]
add wave /testbench_busybear/InstrFName add wave /testbench_busybear/InstrFName
add wave -hex /testbench_busybear/dut/hart/ifu/PCD add wave -hex /testbench_busybear/dut/hart/ifu/PCD
#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD #add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
add wave /testbench_busybear/InstrDName add wave /testbench_busybear/InstrDName
#add wave -divider #add wave -divider
add wave -hex /testbench_busybear/dut/hart/ifu/PCE add wave -hex /testbench_busybear/dut/hart/ifu/PCE
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE ##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE
add wave /testbench_busybear/InstrEName add wave /testbench_busybear/InstrEName
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE #add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE #add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE
add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE
#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE #add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE
#add wave -divider #add wave -divider
add wave -hex /testbench_busybear/dut/hart/ifu/PCM add wave -hex /testbench_busybear/dut/hart/ifu/PCM
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM ##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM
add wave /testbench_busybear/InstrMName add wave /testbench_busybear/InstrMName
#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite #add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite
#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM #add wave -hex /testbench_busybear/dut/hart/dmem/AdrM
#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM #add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM
#add wave -divider #add wave -divider
add wave -hex /testbench_busybear/dut/hart/ifu/PCW add wave -hex /testbench_busybear/dut/hart/ifu/PCW
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW ##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW
add wave /testbench_busybear/InstrWName add wave /testbench_busybear/InstrWName
#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW #add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW #add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW #add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW
#add wave -divider #add wave -divider
##add ww ##add ww
add wave -hex -r /testbench_busybear/* add wave -hex -r /testbench_busybear/*
# #
#-- Set Wave Output Items #-- Set Wave Output Items
#TreeUpdate [SetDefaultTree] #TreeUpdate [SetDefaultTree]
#WaveRestoreZoom {0 ps} {100 ps} #WaveRestoreZoom {0 ps} {100 ps}
#configure wave -namecolwidth 250 #configure wave -namecolwidth 250
#configure wave -valuecolwidth 120 #configure wave -valuecolwidth 120
#configure wave -justifyvalue left #configure wave -justifyvalue left
#configure wave -signalnamewidth 0 #configure wave -signalnamewidth 0
#configure wave -snapdistance 10 #configure wave -snapdistance 10
#configure wave -datasetprefix 0 #configure wave -datasetprefix 0
#configure wave -rowmargin 4 #configure wave -rowmargin 4
#configure wave -childrowmargin 2 #configure wave -childrowmargin 2
#set DefaultRadix hexadecimal #set DefaultRadix hexadecimal
# #
#-- Run the Simulation #-- Run the Simulation
run -all run -all
##quit ##quit

10
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -162,10 +162,10 @@ module testbench_busybear();
$display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
`ERROR `ERROR
end end
if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin //if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin
force dut.hart.ieu.dp.regf.rf[i] = regExpected; // force dut.hart.ieu.dp.regf.rf[i] = regExpected;
release dut.hart.ieu.dp.regf.rf[i]; // release dut.hart.ieu.dp.regf.rf[i];
end //end
end end
end end
end end
@ -348,7 +348,7 @@ module testbench_busybear();
always @(dut.PCF or dut.hart.ifu.InstrF or reset) begin always @(dut.PCF or dut.hart.ifu.InstrF or reset) begin
if(~HWRITE) begin if(~HWRITE) begin
#3; #3;
if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}}) begin if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin
if (dut.PCF !== lastPCF) begin if (dut.PCF !== lastPCF) begin
lastCheckInstrF = CheckInstrF; lastCheckInstrF = CheckInstrF;
lastPC <= dut.PCF; lastPC <= dut.PCF;