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Simplified UM initialization

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This commit is contained in:
David Harris 2022-09-20 04:18:12 -07:00
parent 956011b40b
commit c77ec2aa9c
1 changed files with 2 additions and 2 deletions
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pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -136,9 +136,9 @@ module fdivsqrtiter(
end end
endgenerate endgenerate
// Initialize U to 1 and UM to 0 for square root; U to 0 and UM to -1 for division // Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 for division
assign initU = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0; assign initU = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0;
assign initUM = SqrtE ? 0 : '1; assign initUM = SqrtE ? 0 : {1'b1, {(`DIVb){1'b0}}};
mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, DivStart, UMux); mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, DivStart, UMux);
mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, DivStart, UMMux); mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, DivStart, UMMux);
flopen #(`DIVb+1) UReg(clk, DivStart|DivBusy, UMux, U[0]); flopen #(`DIVb+1) UReg(clk, DivStart|DivBusy, UMux, U[0]);