From 028ffe9f4acb05693fbbfa00ac4da497e341dd38 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 20 Nov 2024 07:23:51 -0800 Subject: [PATCH 01/17] Removing obsolete *** --- config/rv32e/config.vh | 1 - config/rv32gc/config.vh | 1 - config/rv32i/config.vh | 1 - config/rv32imc/config.vh | 1 - config/rv64gc/config.vh | 1 - config/rv64i/config.vh | 1 - examples/fp/fpcalc/fpcalc.c | 2 +- testbench/common/functionName.sv | 2 +- .../WALLY-csr-permission-s-01.reference_output | 9 +++++++++ .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 11 +++++------ .../rv32i_m/privilege/src/WALLY-csr-permission-s-01.S | 9 +++------ .../rv32i_m/privilege/src/WALLY-pma-01.S | 2 +- 12 files changed, 20 insertions(+), 21 deletions(-) diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 4ec0123d1..db0838550 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 0; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index c861759d9..af2032937 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 0; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 01818afc2..ede534f0b 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 1; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 05a8fd242..e9f986a07 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 1; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index b8ed8dc47..4f833178a 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 0; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 94360877f..3a8bae1bc 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16; // Peripheral Physical Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? localparam logic DTIM_SUPPORTED = 1; localparam logic [63:0] DTIM_BASE = 64'h80000000; localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c index 16dcce225..e4638a64b 100644 --- a/examples/fp/fpcalc/fpcalc.c +++ b/examples/fp/fpcalc/fpcalc.c @@ -237,7 +237,7 @@ __uint128_t parseNum(char *num) { if (strlen(num) < 8) size = 2; else if (strlen(num) < 16) size = 4; else if (strlen(num) < 32) size = 8; - else if (strlen(num) < 35) size = 16; // *** will need to increase + else if (strlen(num) < 35) size = 16; else { printf("Error: only half, single, double, or quad precision supported"); exit(1); diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 5a14c84a4..2d257ce32 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -70,7 +70,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( begin if ( pc == 0 ) begin - // *** want to keep the old value for mid and minval + // want to keep the old value for mid and minval mid = 0; return; end diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output index 0a35f7ca0..71ecd9fd2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output @@ -1,4 +1,13 @@ 0000000b # Test 5.2.3.6: ecall from going to S mode from M mode +00000002 # S mode write to mstatush with illegal instruction +00000002 # S mode read from mstatush with illegal instruction +00000bad +00000002 # S mode write to menvcfgh with illegal instruction +00000002 # S mode read from menvcfgh with illegal instruction +00000bad +00000002 # S mode write to mseccfgh with illegal instruction +00000002 # S mode read from mseccfgh with illegal instruction +00000bad 00000002 # S mode write to pmpcfg1 with illegal instruction 00000002 # S mode read from pmpcfg1 with illegal instruction 00000bad diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index f34ca6363..6f7fc8a47 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -117,7 +117,7 @@ cause_store_acc: ret cause_ecall: - // *** ASSUMES you have already gone to the mode you need to call this from. + // ASSUMES you have already gone to the mode you need to call this from. ecall ret @@ -319,7 +319,7 @@ end_trap_triggers: .align 6 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler - // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented + // ASSUMES that a cause value of 0 for an interrupt is unimplemented // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. @@ -337,7 +337,7 @@ trap_handler_\MODE\(): trap_unvectored_\MODE\(): csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. - // *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests + // NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there // save registers on stack before using @@ -707,7 +707,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a .endm .macro READ32 ADDR - // Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value + // Attempt read at ADDR. Write the value read out to the output. Consider adding specific test for reading a non known value // Success outputs: // value read out from ADDR // Fault outputs: @@ -751,7 +751,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // 0x9: test called from S mode // 0xB: test called from M mode // they generally do not fault or cause issues as long as these modes are enabled -// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not? .macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0 li a0, 2 // determine trap handler behavior (go to machine mode) @@ -807,7 +806,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // value read back out from CSR after writing // Fault outputs: // The previous CSR value before write attempt - // *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access + // Most likely 0x2, the mcause for illegal instruction if we don't have write or read access li t5, 0xbad // load bad value to be overwritten by csrr li t4, \VAL csrw \CSR\(), t4 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S index 7194b59a4..af7f6252c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S @@ -32,18 +32,15 @@ TRAP_HANDLER m # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode. -# *** several of these appear not to be implemented in the assembler? -# I get "assembler messages: error: unkown CSR" with many of them. - GOTO_S_MODE 0x0, 0x0 # Attempt to write 0x111 to each of these CSRs and read the value back # should result in an illegal instruction for the write and read, respectively # High-bit versions storing the upper 32 bits of some CSRs for RV32 -# WRITE_READ_CSR mstatush 0x111 # *** these appear not to be implemented in GCC -# WRITE_READ_CSR menvcfgh 0x111 -# WRITE_READ_CSR mseccfgh 0x111 +WRITE_READ_CSR mstatush 0x111 # not supported in rv32 +WRITE_READ_CSR menvcfgh 0x111 +WRITE_READ_CSR mseccfgh 0x111 WRITE_READ_CSR pmpcfg1 0x111 WRITE_READ_CSR pmpcfg3 0x111 WRITE_READ_CSR mcycleh 0x111 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S index 0c1c7bbb2..2c58b0db8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S @@ -66,7 +66,7 @@ test_cases: # --------------------------------------------------------------------------------------------- # =========== test 12.3.2.1 PMAs: Memory Access Size, Type protection test =========== -# Tests memory load, store, and execute permissions based on table 12.3 in the *** riscv book, copied below +# Tests memory load, store, and execute permissions # | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic | # | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO | From 123fdd29cfcbd9a5eb9f3f09a617abad0d75cd31 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 20 Nov 2024 16:30:49 -0800 Subject: [PATCH 02/17] Updated tool portion of README --- README.md | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 40dc08d51..0a060f510 100644 --- a/README.md +++ b/README.md @@ -135,11 +135,17 @@ export VCS_HOME=.. # Change this for your path to Synopsys VCS Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access. -Siemens Questa is the primary tool utilized for simulating and validating Wally. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license. +Verilator is an open-source Verilog simulator. It is fast and free. Run Wally on the riscv-arch-test suite using Verilator with: + +``` +regression-wally +``` + +Running code or functional coverage simulations or lock-step presently require commercial tools. Siemens Questa is the primary tool utilized for simulating and validating Wally. Synopsys VCS also can run regression-wally and lock-step simulation. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license. Note: Some EDA tools utilize `LM_LICENSE_FILE` for their environmental variable to point to their license server. Some operating systems may also utilize `MGLS_LICENSE_FILE` instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license. -Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels. +Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Red Hat Enterprise Linux (and its free Rocky clone) typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. ### Siemens Questa From 05189d102ac5de8fa778ecd2836b1c00c8035e7c Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 26 Nov 2024 22:09:11 -0800 Subject: [PATCH 03/17] Modifying tracer toward being able to run non-gc configurations in lockstep --- testbench/common/wallyTracer.sv | 355 +++++++++++++++++--------------- testbench/testbench.sv | 14 +- 2 files changed, 195 insertions(+), 174 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index a32417737..51f0d302a 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -95,11 +95,19 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign FlushW = testbench.dut.core.FlushW; assign TrapM = testbench.dut.core.TrapM; assign HaltM = testbench.DCacheFlushStart; - assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW; - assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL; - assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; - assign wfiM = testbench.dut.core.priv.priv.wfiM; - assign InterruptM = testbench.dut.core.priv.priv.InterruptM; + if (P.ZICSR_SUPPORTED) begin + assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW; + assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL; + assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; + assign wfiM = testbench.dut.core.priv.priv.wfiM; + assign InterruptM = testbench.dut.core.priv.priv.InterruptM; + end else begin + assign PrivilegeModeW = 2'b11; + assign STATUS_SXL = 0; + assign STATUS_UXL = 0; + assign wfiM = 0; + assign InterruptM = 0; + end //For VM Verification assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; @@ -116,181 +124,185 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic valid; - always_comb begin - // Since we are detected the CSR change by comparing the old value we need to - // ensure the CSR is detected when the pipeline's Writeback stage is not - // stalled. If it is stalled we want CSRArray to hold the old value. - if(valid) begin - // PMPCFG CSRs (space is 0-15 3a0 - 3af) - localparam inc = P.XLEN == 32 ? 4 : 8; - int i, i4, i8, csrid; - logic [P.XLEN-1:0] pmp; + if (P.ZICSR_SUPPORTED) begin + always_comb begin + // Since we are detected the CSR change by comparing the old value we need to + // ensure the CSR is detected when the pipeline's Writeback stage is not + // stalled. If it is stalled we want CSRArray to hold the old value. + if(valid) begin + // PMPCFG CSRs (space is 0-15 3a0 - 3af) + localparam inc = P.XLEN == 32 ? 4 : 8; + int i, i4, i8, csrid; + logic [P.XLEN-1:0] pmp; - for (i=0; i Date: Tue, 26 Nov 2024 22:10:18 -0800 Subject: [PATCH 04/17] Adding ExceptionsInstr coverage --- config/rv32gc/coverage.svh | 3 ++- config/rv64gc/coverage.svh | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 0403b7e4b..ee996e11c 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -44,4 +44,5 @@ `include "EndianU_coverage.svh" `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" -`include "ExceptionsM_coverage.svh" \ No newline at end of file +`include "ExceptionsM_coverage.svh" +`include "ExceptionsInstr_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index e7c574020..a2d691e4e 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -44,6 +44,7 @@ `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" `include "ExceptionsM_coverage.svh" +`include "ExceptionsInstr_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 8a910aabf4a0cecea1f783a1458672fcc2eb5096 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 27 Nov 2024 05:42:39 -0800 Subject: [PATCH 05/17] Documentation and comment fixes --- README.md | 5 +++-- bin/wally-distro-check.sh | 2 +- .../rv32i_m/privilege/src/WALLY-csr-permission-s-01.S | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 2a23f66d2..0f560f63a 100644 --- a/README.md +++ b/README.md @@ -71,7 +71,8 @@ Then fork and clone the repo, source setup, make the tests and run regression > This section describes the open source toolchain installation. ### Compatibility -The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS), Debian (versions 11 and 12), and Red Hat/Rocky/AlmaLinux (versions 8 and 9). Only the latest minor release of each major version is tested. +The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS), Debian (versions 11 and 12), Red Hat/Rocky/AlmaLinux (versions 8 and 9), +and SUSE version 15.6. Only the latest minor release of each major version is tested. > [!WARNING] > - Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler. @@ -145,7 +146,7 @@ Running code or functional coverage simulations or lock-step presently require c Note: Some EDA tools utilize `LM_LICENSE_FILE` for their environmental variable to point to their license server. Some operating systems may also utilize `MGLS_LICENSE_FILE` instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license. -Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Red Hat Enterprise Linux (and its free Rocky clone) typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. +Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Red Hat Enterprise Linux (and its free Rocky clone) and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. ### Siemens Questa diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index db0699fd2..f08f5e2e2 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -96,7 +96,7 @@ elif [[ "$ID" == debian || "$ID_LIKE" == *debian* ]]; then exit 1 fi else - printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally installation script is currently only compatible with Ubuntu, Debian, and Red Hat family " \ + printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally installation script is currently only compatible with Ubuntu, Debian, SUSE, and Red Hat family " \ "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ "commands in this script, but it is likely that some will need to be altered." exit 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S index af7f6252c..a222a37a5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S @@ -38,7 +38,7 @@ GOTO_S_MODE 0x0, 0x0 # should result in an illegal instruction for the write and read, respectively # High-bit versions storing the upper 32 bits of some CSRs for RV32 -WRITE_READ_CSR mstatush 0x111 # not supported in rv32 +WRITE_READ_CSR mstatush 0x111 WRITE_READ_CSR menvcfgh 0x111 WRITE_READ_CSR mseccfgh 0x111 WRITE_READ_CSR pmpcfg1 0x111 From 2ad039aadc6f1ab8d0fa0e1a5a1d4bea1074ff06 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 27 Nov 2024 06:21:37 -0800 Subject: [PATCH 06/17] Reversed adding exceptionsInstr; using exceptionsM instead --- config/rv32gc/coverage.svh | 1 - config/rv64gc/coverage.svh | 1 - 2 files changed, 2 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index ee996e11c..115dbd5f1 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -45,4 +45,3 @@ `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" `include "ExceptionsM_coverage.svh" -`include "ExceptionsInstr_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index a2d691e4e..e7c574020 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -44,7 +44,6 @@ `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" `include "ExceptionsM_coverage.svh" -`include "ExceptionsInstr_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 37c68798056f652a99dcea69e1b8f1e851cc3404 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 27 Nov 2024 15:12:11 -0800 Subject: [PATCH 07/17] Fixed decoder bug that doesn't throw illegal instruction exception for RV32 immediate shifts by more than 31 --- src/ieu/bmu/bmuctrl.sv | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index d4a8afe23..e55c24faa 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -152,12 +152,13 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( endcase end if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used - casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw, slliw - endcase + if (P.XLEN == 64 | !Funct7D[0]) // rv32i shifts cannot shift by more than 31 + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw, slliw + endcase if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip casez({OpD,Funct7D, Funct3D}) From 9116ffa45d52e627a656c4b90f145ad7a18b4e62 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 28 Nov 2024 13:36:31 -0800 Subject: [PATCH 08/17] Fixed Issue #1147 that w-type shifts do not throw illegal instruction trap in RV32GC --- src/ieu/bmu/bmuctrl.sv | 15 ++++++++++----- src/ieu/controller.sv | 1 - 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index e55c24faa..f9c524ec9 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -152,12 +152,17 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( endcase end if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used - if (P.XLEN == 64 | !Funct7D[0]) // rv32i shifts cannot shift by more than 31 + if (P.XLEN == 64 | !Funct7D[0]) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw, slliw + // rv32i shifts cannot shift by more than 31. w-type shifts only supported in RV64 + 17'b0110011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sll + 17'b0110011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl + 17'b0010011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // slli + 17'b0010011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli + 17'b0111011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sllw + 17'b0111011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw + 17'b0011011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // slliw + 17'b0011011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw endcase if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 19f96c98d..4f1f778c1 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -300,7 +300,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( // Squash control signals if coming from an illegal compressed instruction // On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them. assign IllegalERegAdrD = P.E_SUPPORTED & P.ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; - //assign IllegalBaseInstrD = 1'b0; assign {BaseRegWriteD, PreImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, CMOD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; From f1072e46e118d76b8fc40f577cd7b3cd9f994ed9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 28 Nov 2024 14:40:09 -0800 Subject: [PATCH 09/17] fcvt to/fron long only allowed in RV64 --- src/fpu/fctrl.sv | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index d04fc45fa..cd2f2d5d7 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -196,54 +196,54 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( 7'b1101000: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.s.w w->s 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.s.wu wu->s - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.s.l l->s - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.s.lu lu->s + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.s.l l->s + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.s.lu lu->s endcase 7'b1100000: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.s s->w 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.s s->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.s s->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.s s->lu + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.s s->l + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.s s->lu endcase 7'b1101001: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.d.w w->d 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.d.wu wu->d - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.d.l l->d - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.d.lu lu->d + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.d.l l->d + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.d.lu lu->d endcase 7'b1100001: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.d d->w 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.d d->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.d d->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.d d->lu + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.d d->l + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.d d->lu 5'b01000: if (P.ZFA_SUPPORTED & P.D_SUPPORTED & Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_1_0; // fcvtmod.w.d (Zfa) endcase 7'b1101010: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.h.w w->h 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.h.wu wu->h - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.h.l l->h - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.h.lu lu->h + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.h.l l->h + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.h.lu lu->h endcase 7'b1100010: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.h h->w 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.h h->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.h h->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.h h->lu + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.h h->l + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.h h->lu endcase // Not covered in testing because rv64gc does not support quad precision // coverage off 7'b1101011: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.q.w w->q 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.q.wu wu->q - 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.q.l l->q - 5'b00011: ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.q.lu lu->q + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.q.l l->q + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.q.lu lu->q endcase 7'b1100011: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.q q->w 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.q q->wu - 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.q q->l - 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.q q->lu + 5'b00010: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.q q->l + 5'b00011: if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.q q->lu endcase // coverage off // Not covered in testing because rv64gc is not RV64Q or RV32D From 3f6611dd3a7503e0757112667a0ddd60cc73c4dd Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 28 Nov 2024 14:47:58 -0800 Subject: [PATCH 10/17] Fixed fmv.d.x / fmv.x.d only on RV64 --- src/fpu/fctrl.sv | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index cd2f2d5d7..2b8dbc411 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -153,18 +153,20 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( endcase 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0_0_0; // fclass - else if (Funct3D == 3'b000 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h/q fp to int register - else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001) - ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d (Zfa) + else if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin + if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) + ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h fp to int register (double only in RV64) + end else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001) + ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d (Zfa) // Q not supported in RV64GC // coverage off else if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct7D[1:0] == 2'b11 & Funct3D == 3'b000 & Rs2D == 5'b00001) - ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q (Zfa) + ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q (Zfa) // coverage on - 7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h/q.x int to fp reg - else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001) + 7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin + if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) + ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h.x int to fp reg (double only in RV64) + end else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001) ControlsD = `FCTRLW'b1_0_00_00_111_0_0_0_1_0; // fli (Zfa) 7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00) ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_0_0; // fcvt.s.(d/q/h) From 722dc9bfdaa446470879c8172a292a65a87364e2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 28 Nov 2024 16:34:43 -0800 Subject: [PATCH 11/17] Throw illegal instruction for RV64 W-type shifts with amounts > 31 --- src/ieu/controller.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 4f1f778c1..75dbf2b6a 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -181,8 +181,8 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign Funct7ZeroD = (Funct7D == 7'b0000000); // most R-type instructions assign Funct7b5D = (Funct7D == 7'b0100000); // srai, sub assign FunctCZeroD = (Funct3D == 3'b101 | Funct3D == 3'b111) & (Funct7D == 7'b0000111) & P.ZICOND_SUPPORTED; // czero.eqz or czero.nez - assign Funct7ShiftZeroD = (P.XLEN==64) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD; - assign Funct7Shiftb5D = (P.XLEN==64) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D; + assign Funct7ShiftZeroD = (P.XLEN==64 & ~OpD[3]) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD; // 64-bit logical shifts allowed on XLEN=64, non-W + assign Funct7Shiftb5D = (P.XLEN==64 & ~OpD[3]) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D; // 64-bit arithmetic shifts allowed on XLEN=64, non-W assign IShiftD = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms assign INoShiftD = ((Funct3D != 3'b001) & (Funct3D != 3'b101)); assign IFunctD = IShiftD | INoShiftD; From cf47dd7e6bf7b1d60dc5d8297f3622181c47abac Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 05:58:14 -0800 Subject: [PATCH 12/17] Fixed bmu shift decode logic: bad funct7 for variable shifts, commented better, removed unnecessary guard --- src/ieu/bmu/bmuctrl.sv | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index f9c524ec9..a551179e9 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -152,18 +152,19 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( endcase end if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used - if (P.XLEN == 64 | !Funct7D[0]) - casez({OpD, Funct7D, Funct3D}) - // rv32i shifts cannot shift by more than 31. w-type shifts only supported in RV64 - 17'b0110011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sll - 17'b0110011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl - 17'b0010011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // slli - 17'b0010011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli - 17'b0111011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sllw - 17'b0111011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw - 17'b0011011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // slliw - 17'b0011011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw - endcase + casez({OpD, Funct7D, Funct3D}) + // variable shifts don't encode shift amount in funct7 + 17'b0110011_0000000_001: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sll + 17'b0110011_0?00000_101: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl + // Immediate Shifts by more than 32 (Funct7[0]) are only supported in RV64 + 17'b0010011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // slli + 17'b0010011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli + // w-type shifts only supported in RV64 and must have Funct7[0] = 0 because the shift amount is < 32 + 17'b0111011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sllw + 17'b0111011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw + 17'b0011011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // slliw + 17'b0011011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw + endcase if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip casez({OpD,Funct7D, Funct3D}) From 58bfc27c63135011f2b25a3767ce625b18f853fb Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 11:20:12 -0800 Subject: [PATCH 13/17] Fixed decoder for illegal 0b1e0c33 issue #1152 --- src/ieu/bmu/bmuctrl.sv | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index a551179e9..fe781e78b 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -119,13 +119,11 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( if (P.ZBC_SUPPORTED) casez({OpD, Funct7D, Funct3D}) 17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_0_1_0_0_0_0_0; // clmulr - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh + 17'b0110011_0000101_0?1: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh endcase if (P.ZBKC_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh - // 17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul - // 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_0_1_0_0_0_0_0; // clmulh + 17'b0110011_0000101_0?1: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh endcase end From 155d1d511b56632c21e3b22fd849b8cd34aa2467 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 11:39:24 -0800 Subject: [PATCH 14/17] Fixed funct7 code for sinval.vma (issue #1154) --- src/privileged/privdec.sv | 2 +- testbench/common/instrNameDecTB.sv | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index 6321413d4..99380e63f 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -59,7 +59,7 @@ module privdec import cvw::*; #(parameter cvw_t P) ( // svinval instructions // any svinval instruction is treated as sfence.vma on Wally - assign sinvalvmaM = (InstrM[31:25] == 7'b0001001); + assign sinvalvmaM = (InstrM[31:25] == 7'b0001011); assign sfencewinvalM = (InstrM[31:20] == 12'b000110000000) & rs1zeroM; assign sfenceinvalirM = (InstrM[31:20] == 12'b000110000001) & rs1zeroM; assign invalM = P.SVINVAL_SUPPORTED & (sinvalvmaM | sfencewinvalM | sfenceinvalirM); diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv index 80f6ed607..ae970513f 100644 --- a/testbench/common/instrNameDecTB.sv +++ b/testbench/common/instrNameDecTB.sv @@ -219,6 +219,10 @@ module instrNameDecTB( else if (imm == 258) name = "SRET"; else if (imm == 770) name = "MRET"; else if (funct7 == 9) name = "SFENCE.VMA"; + else if (funct7 == 11) name = "SINVAL.VMA"; + else if (funct7 == 12 & rs2 == 0) name = "SFENCE.W.INVAL"; + else if (funct7 == 12 & rs2 == 1) name = "SFENCE.INVAL.IR"; + else if (imm == 259) name = "WFI"; else if (imm == 261) name = "WFI"; else name = "ILLEGAL"; 10'b1110011_001: name = "CSRRW"; From ec3143f01471840134064e8b20c20a8e53a33fe5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 12:03:14 -0800 Subject: [PATCH 15/17] Updated warning in ramxdetector --- testbench/common/ramxdetector.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/common/ramxdetector.sv b/testbench/common/ramxdetector.sv index c600cff8c..fac34fb43 100644 --- a/testbench/common/ramxdetector.sv +++ b/testbench/common/ramxdetector.sv @@ -39,7 +39,7 @@ module ramxdetector #(parameter XLEN, LLEN) ( /* verilator lint_off WIDTHXZEXPAND */ if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin /* verilator lint_on WIDTHXZEXPAND */ - $display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests."); + $display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests."); $display(" PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM); //$stop; end From 9d3e82d3ec17bfc0c61d4658759dca821531082e Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 12:05:00 -0800 Subject: [PATCH 16/17] Updated imperas.ic files so rv32 follows rv64 --- config/rv32gc/imperas.ic | 16 +++++++++++----- config/rv64gc/imperas.ic | 4 +--- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index 2ba3c1280..0c3f2e2ea 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -9,7 +9,7 @@ #--showcommands # Core settings ---variant RV32GC # for RV32GC +--variant RV32GCK # for RV32GC --override cpu/priv_version=1.12 --override cpu/user_version=20191213 # arch @@ -59,7 +59,7 @@ #--override cpu/instret_undefined=T #--override cpu/hpmcounter_undefined=T -## context registers not implemented +# context registers not implemented #--override cpu/scontext_undefined=True #--override cpu/mcontext_undefined=True @@ -69,9 +69,14 @@ #--override cpu/Zicfilp=F --override cpu/trigger_num=0 # disable CSRs 7a0-7a8 ---override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions +# For code coverage, don't produce pseudoinstructions +--override no_pseudo_inst=T ---override show_c_prefix=T # Show "c." with compressed instructions +# Show "c." with compressed instructions +--override show_c_prefix=T + +# nonratified mnoise register not implemented +--override cpu/mnoise_undefined=T # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag #--override cpu/ecode_mask=0x8000000F # for RV32 @@ -80,7 +85,8 @@ # Debug mode not yet supported --override cpu/debug_mode=none - +# Zkr entropy source and seed register not supported. +--override cpu/Zkr=F --override cpu/reset_address=0x80000000 diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic index 9ba14f2f0..19a7515a5 100644 --- a/config/rv64gc/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -73,7 +73,7 @@ # Show "c." with compressed instructions --override show_c_prefix=T -# nonratified mnosie register not implemented +# nonratified mnoise register not implemented --override cpu/mnoise_undefined=T # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag @@ -86,8 +86,6 @@ # Zkr entropy source and seed register not supported. --override cpu/Zkr=F - - --override cpu/reset_address=0x80000000 --override cpu/unaligned=T # Zicclsm (should be true) From 11272984bd42afdb8796e92063f06628d568db15 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Nov 2024 14:49:48 -0800 Subject: [PATCH 17/17] Added ExceptionsZc illegal instruction coverage --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 115dbd5f1..90593e0f5 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -45,3 +45,4 @@ `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" `include "ExceptionsM_coverage.svh" +`include "ExceptionsZc_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index e7c574020..6aba1ac9a 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -44,6 +44,7 @@ `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" `include "ExceptionsM_coverage.svh" +`include "ExceptionsZc_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh"