mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed lint warning
This commit is contained in:
Katherine Parry
parent
f5bfdf46db
commit
c74d26eea4
1024
wally-pipelined/config/rv32icfd/BTBPredictor.txt
Normal file
1024
wally-pipelined/config/rv32icfd/BTBPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
1024
wally-pipelined/config/rv32icfd/twoBitPredictor.txt
Normal file
1024
wally-pipelined/config/rv32icfd/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
106
wally-pipelined/config/rv32icfd/wally-config.vh
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106
wally-pipelined/config/rv32icfd/wally-config.vh
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@ -0,0 +1,106 @@
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//////////////////////////////////////////
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// wally-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// include shared configuration
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`include "wally-shared.vh"
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`define BUILDROOT 0
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`define BUSYBEAR 0
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 32
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`define MISA (32'h00000104 | 1 << 5 | 1 << 20 | 1 << 18 | 1 << 12)
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`define ZCSR_SUPPORTED 1
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`define COUNTERS 32
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`define ZCOUNTERS_SUPPORTED 1
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// Microarchitectural Features
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DCACHE 0
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`define MEM_DTIM 1
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`define MEM_ICACHE 0
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRIES 32
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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// Address space
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`define RESET_VECTOR 32'h80000000
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
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`define BOOTTIM_SUPPORTED 1'b1
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`define BOOTTIM_BASE 34'h00001000
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`define BOOTTIM_RANGE 34'h00000FFF
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`define TIM_SUPPORTED 1'b1
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`define TIM_BASE 34'h80000000
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`define TIM_RANGE 34'h07FFFFFF
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`define CLINT_SUPPORTED 1'b1
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`define CLINT_BASE 34'h02000000
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`define CLINT_RANGE 34'h0000FFFF
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`define GPIO_SUPPORTED 1'b1
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`define GPIO_BASE 34'h10012000
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`define GPIO_RANGE 34'h000000FF
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`define UART_SUPPORTED 1'b1
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`define UART_BASE 34'h10000000
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`define UART_RANGE 34'h00000007
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`define PLIC_SUPPORTED 1'b1
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`define PLIC_BASE 34'h0C000000
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`define PLIC_RANGE 34'h03FFFFFF
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// Bus Interface width
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`define AHBW 32
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 1
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// Hardware configuration
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`define UART_PRESCALE 1
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// Interrupt configuration
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`define PLIC_NUM_SRC 4
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// comment out the following if >=32 sources
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`define PLIC_NUM_SRC_LT_32
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 4
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`define TWO_BIT_PRELOAD "../config/rv32icfd/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv32icfd/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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@ -1,109 +1,3 @@
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// //////////////////////////////////////////
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// // wally-config.vh
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// //
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// // Written: David_Harris@hmc.edu 4 January 2021
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// // Modified:
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// //
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// // Purpose: Specify which features are configured
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// // Macros to determine which modes are supported based on MISA
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// //
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// // A component of the Wally configurable RISC-V project.
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// //
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// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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// //
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// // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// // files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// // modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// // is furnished to do so, subject to the following conditions:
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// //
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// // The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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// //
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// // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// // OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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// ///////////////////////////////////////////
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// // include shared configuration
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// `include "wally-shared.vh"
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// `define BUILDROOT 0
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// `define BUSYBEAR 0
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// // RV32 or RV64: XLEN = 32 or 64
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// `define XLEN 32
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// `define MISA (32'h00000104 | 1 << 5 | 1 << 20 | 1 << 18 | 1 << 12)
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// `define ZCSR_SUPPORTED 1
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// `define COUNTERS 32
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// `define ZCOUNTERS_SUPPORTED 1
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// // Microarchitectural Features
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// `define UARCH_PIPELINED 1
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// `define UARCH_SUPERSCALR 0
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// `define UARCH_SINGLECYCLE 0
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// `define MEM_DCACHE 0
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// `define MEM_DTIM 1
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// `define MEM_ICACHE 0
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// `define MEM_VIRTMEM 1
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// `define VECTORED_INTERRUPTS_SUPPORTED 1
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// `define ITLB_ENTRIES 32
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// `define DTLB_ENTRIES 32
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// // Legal number of PMP entries are 0, 16, or 64
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// `define PMP_ENTRIES 16
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// // Address space
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// `define RESET_VECTOR 32'h80000000
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// // Peripheral Addresses
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// // Peripheral memory space extends from BASE to BASE+RANGE
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// // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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// // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
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// `define BOOTTIM_SUPPORTED 1'b1
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// `define BOOTTIM_BASE 34'h00001000
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// `define BOOTTIM_RANGE 34'h00000FFF
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// `define TIM_SUPPORTED 1'b1
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// `define TIM_BASE 34'h80000000
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// `define TIM_RANGE 34'h07FFFFFF
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// `define CLINT_SUPPORTED 1'b1
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// `define CLINT_BASE 34'h02000000
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// `define CLINT_RANGE 34'h0000FFFF
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// `define GPIO_SUPPORTED 1'b1
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// `define GPIO_BASE 34'h10012000
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// `define GPIO_RANGE 34'h000000FF
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// `define UART_SUPPORTED 1'b1
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// `define UART_BASE 34'h10000000
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// `define UART_RANGE 34'h00000007
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// `define PLIC_SUPPORTED 1'b1
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// `define PLIC_BASE 34'h0C000000
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// `define PLIC_RANGE 34'h03FFFFFF
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// // Bus Interface width
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// `define AHBW 32
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// // Test modes
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// // Tie GPIO outputs back to inputs
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// `define GPIO_LOOPBACK_TEST 1
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// // Hardware configuration
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// `define UART_PRESCALE 1
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// // Interrupt configuration
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// `define PLIC_NUM_SRC 4
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// // comment out the following if >=32 sources
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// `define PLIC_NUM_SRC_LT_32
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// `define PLIC_GPIO_ID 3
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// `define PLIC_UART_ID 4
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// `define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
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// `define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
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// `define BPRED_ENABLED 1
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// `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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// `define TESTSBP 0
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//////////////////////////////////////////
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// wally-config.vh
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//
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3
wally-pipelined/regression/sim-wally-batch-rv32icfd
Executable file
3
wally-pipelined/regression/sim-wally-batch-rv32icfd
Executable file
@ -0,0 +1,3 @@
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vsim -c <<!
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do wally-pipelined-batch-rv32icfd.do ../config/rv32icfd rv32icfd
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!
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1
wally-pipelined/regression/sim-wally-rv32icfd
Executable file
1
wally-pipelined/regression/sim-wally-rv32icfd
Executable file
@ -0,0 +1 @@
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vsim -do wally-pipelined-rv32icfd.do
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42
wally-pipelined/regression/wally-pipelined-batch-rv32icfd.do
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42
wally-pipelined/regression/wally-pipelined-batch-rv32icfd.do
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@ -0,0 +1,42 @@
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# wally-pipelined-batch.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-pipelined-batch.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined-batch.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined-batch.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work_$2] {
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vdel -lib work_$2 -all
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}
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vlib work_$2
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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switch $argc {
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0 {vlog +incdir+../config/rv32icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
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1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
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2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
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}
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt work_$2.testbench -work work_$2 -o workopt_$2
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vsim -lib work_$2 workopt_$2
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run -all
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quit
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50
wally-pipelined/regression/wally-pipelined-rv32icfd.do
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50
wally-pipelined/regression/wally-pipelined-rv32icfd.do
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@ -0,0 +1,50 @@
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# wally-pipelined.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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# do wally-pipelined.do ../config/rv32ic
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switch $argc {
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0 {vlog +incdir+../config/rv32icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
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1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
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}
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench -o workopt
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vsim workopt
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view wave
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-- display input and output signals as hexidecimal values
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do ./wave-dos/default-waves.do
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-- Run the Simulation
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#run 5000
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run -all
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#quit
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noview ../testbench/testbench-imperas.sv
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view wave
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@ -93,7 +93,7 @@ module fcvt (
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logic [8:0] i;
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always_comb begin
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i = 0;
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while (~PosInt[64-1-i] && i <= `XLEN) i = i+1; // search for leading one
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while (~PosInt[64-1-i] && i < `XLEN) i = i+1; // search for leading one
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LZResP = i+1; // compute shift count
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end
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@ -153,7 +153,7 @@ module fpu (
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flopenrc #(1) DECtrlRegE1(clk, reset, FlushE, ~StallE, FDivStartD, FDivStartE);
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flopenrc #(15) DECtrlRegE2(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]},
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{Adr1E, Adr2E, Adr3E});
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flopenrc #(22) DECtrlReg3(clk, reset, FlushE, ~StallE,
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flopenrc #(17) DECtrlReg3(clk, reset, FlushE, ~StallE,
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{FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD},
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{FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE});
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@ -242,7 +242,7 @@ module fpu (
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flopenrc #(64) EMRegCvt1(clk, reset, FlushM, ~StallM, CvtResE, CvtResM);
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flopenrc #(5) EMRegCvt2(clk, reset, FlushM, ~StallM, CvtFlgE, CvtFlgM);
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flopenrc #(22) EMCtrlReg(clk, reset, FlushM, ~StallM,
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flopenrc #(17) EMCtrlReg(clk, reset, FlushM, ~StallM,
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{FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE},
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{FRegWriteM, FResultSelM, FResSelM, FIntResSelM, FrmM, FmtM, FOpCtrlM, FWriteIntM});
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@ -272,7 +272,7 @@ module fpu (
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flopenrc #(64) MWRegClass2(clk, reset, FlushW, ~StallW, FResM, FResW);
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flopenrc #(11) MWCtrlReg(clk, reset, FlushW, ~StallW,
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flopenrc #(6) MWCtrlReg(clk, reset, FlushW, ~StallW,
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{FRegWriteM, FResultSelM, FmtM, FWriteIntM},
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{FRegWriteW, FResultSelW, FmtW, FWriteIntW});
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@ -57,12 +57,8 @@ module testbench();
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string tests32f[] = '{
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"rv32f/I-FADD-S-01", "2000",
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"rv32f/I-FCLASS-S-01", "2000",
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"rv32f/I-FCVT-S-L-01", "2000",
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"rv32f/I-FCVT-S-LU-01", "2000",
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"rv32f/I-FCVT-S-W-01", "2000",
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"rv32f/I-FCVT-S-WU-01", "2000",
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"rv32f/I-FCVT-L-S-01", "2000",
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"rv32f/I-FCVT-LU-S-01", "2000",
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"rv32f/I-FCVT-W-S-01", "2000",
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"rv32f/I-FCVT-WU-S-01", "2000",
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// "rv32f/I-FDIV-S-01", "2000",
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