Fixed lint warning

wally-pipelined/config/rv32icfd/wally-config.vh

@@ -0,0 +1,106 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define BUILDROOT 0
+`define BUSYBEAR 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 32
+
+`define MISA (32'h00000104 | 1 << 5 | 1 << 20 | 1 << 18 | 1 << 12)
+`define ZCSR_SUPPORTED 1
+`define COUNTERS 32
+`define ZCOUNTERS_SUPPORTED 1
+
+// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+`define MEM_DCACHE 0
+`define MEM_DTIM 1
+`define MEM_ICACHE 0
+`define MEM_VIRTMEM 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1
+
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 16
+
+// Address space
+`define RESET_VECTOR 32'h80000000
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+`define BOOTTIM_SUPPORTED 1'b1
+`define BOOTTIM_BASE   34'h00001000 
+`define BOOTTIM_RANGE  34'h00000FFF
+`define TIM_SUPPORTED 1'b1
+`define TIM_BASE       34'h80000000
+`define TIM_RANGE      34'h07FFFFFF
+`define CLINT_SUPPORTED 1'b1
+`define CLINT_BASE  34'h02000000
+`define CLINT_RANGE 34'h0000FFFF
+`define GPIO_SUPPORTED 1'b1
+`define GPIO_BASE   34'h10012000
+`define GPIO_RANGE  34'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   34'h10000000
+`define UART_RANGE  34'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   34'h0C000000
+`define PLIC_RANGE  34'h03FFFFFF
+
+// Bus Interface width
+`define AHBW 32
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 4
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 4
+
+`define TWO_BIT_PRELOAD "../config/rv32icfd/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/rv32icfd/BTBPredictor.txt"
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0

wally-pipelined/config/rv64icfd/wally-config.vh

@@ -1,109 +1,3 @@
-// //////////////////////////////////////////
-// // wally-config.vh
-// //
-// // Written: David_Harris@hmc.edu 4 January 2021
-// // Modified: 
-// //
-// // Purpose: Specify which features are configured
-// //          Macros to determine which modes are supported based on MISA
-// // 
-// // A component of the Wally configurable RISC-V project.
-// // 
-// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-// //
-// // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// // files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// // modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// // is furnished to do so, subject to the following conditions:
-// //
-// // The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-// //
-// // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// // OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-// ///////////////////////////////////////////
-
-// // include shared configuration
-// `include "wally-shared.vh"
-
-// `define BUILDROOT 0
-// `define BUSYBEAR 0
-
-// // RV32 or RV64: XLEN = 32 or 64
-// `define XLEN 32
-
-// `define MISA (32'h00000104 | 1 << 5 | 1 << 20 | 1 << 18 | 1 << 12)
-// `define ZCSR_SUPPORTED 1
-// `define COUNTERS 32
-// `define ZCOUNTERS_SUPPORTED 1
-
-// // Microarchitectural Features
-// `define UARCH_PIPELINED 1
-// `define UARCH_SUPERSCALR 0
-// `define UARCH_SINGLECYCLE 0
-// `define MEM_DCACHE 0
-// `define MEM_DTIM 1
-// `define MEM_ICACHE 0
-// `define MEM_VIRTMEM 1
-// `define VECTORED_INTERRUPTS_SUPPORTED 1
-
-// `define ITLB_ENTRIES 32
-// `define DTLB_ENTRIES 32
-
-// // Legal number of PMP entries are 0, 16, or 64
-// `define PMP_ENTRIES 16
-
-// // Address space
-// `define RESET_VECTOR 32'h80000000
-
-// // Peripheral Addresses
-// // Peripheral memory space extends from BASE to BASE+RANGE
-// // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-// // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-// `define BOOTTIM_SUPPORTED 1'b1
-// `define BOOTTIM_BASE   34'h00001000 
-// `define BOOTTIM_RANGE  34'h00000FFF
-// `define TIM_SUPPORTED 1'b1
-// `define TIM_BASE       34'h80000000
-// `define TIM_RANGE      34'h07FFFFFF
-// `define CLINT_SUPPORTED 1'b1
-// `define CLINT_BASE  34'h02000000
-// `define CLINT_RANGE 34'h0000FFFF
-// `define GPIO_SUPPORTED 1'b1
-// `define GPIO_BASE   34'h10012000
-// `define GPIO_RANGE  34'h000000FF
-// `define UART_SUPPORTED 1'b1
-// `define UART_BASE   34'h10000000
-// `define UART_RANGE  34'h00000007
-// `define PLIC_SUPPORTED 1'b1
-// `define PLIC_BASE   34'h0C000000
-// `define PLIC_RANGE  34'h03FFFFFF
-
-// // Bus Interface width
-// `define AHBW 32
-
-// // Test modes
-
-// // Tie GPIO outputs back to inputs
-// `define GPIO_LOOPBACK_TEST 1
-
-// // Hardware configuration
-// `define UART_PRESCALE 1
-
-// // Interrupt configuration
-// `define PLIC_NUM_SRC 4
-// // comment out the following if >=32 sources
-// `define PLIC_NUM_SRC_LT_32
-// `define PLIC_GPIO_ID 3
-// `define PLIC_UART_ID 4
-
-// `define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
-// `define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
-// `define BPRED_ENABLED 1
-// `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
-// `define TESTSBP 0
 //////////////////////////////////////////
 // wally-config.vh
 //

wally-pipelined/regression/sim-wally-batch-rv32icfd

@@ -0,0 +1,3 @@
+vsim -c <<!
+do wally-pipelined-batch-rv32icfd.do ../config/rv32icfd rv32icfd
+!

wally-pipelined/regression/sim-wally-rv32icfd

@@ -0,0 +1 @@
+vsim -do wally-pipelined-rv32icfd.do

wally-pipelined/regression/wally-pipelined-batch-rv32icfd.do

@@ -0,0 +1,42 @@
+# wally-pipelined-batch.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# Use this wally-pipelined-batch.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined-batch.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined-batch.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work_$2] {
+    vdel -lib work_$2 -all
+}
+vlib work_$2
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# default to config/rv64ic, but allow this to be overridden at the command line.  For example:
+switch $argc {
+    0 {vlog +incdir+../config/rv32icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
+    1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv  ../src/*/*.sv -suppress 2583}
+    2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv  ../src/*/*.sv -suppress 2583}
+}
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+vopt work_$2.testbench -work work_$2 -o workopt_$2
+vsim -lib work_$2 workopt_$2
+
+run -all
+quit

wally-pipelined/regression/wally-pipelined-rv32icfd.do

@@ -0,0 +1,50 @@
+# wally-pipelined.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# Use this wally-pipelined.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# default to config/rv64ic, but allow this to be overridden at the command line.  For example:
+# do wally-pipelined.do ../config/rv32ic
+switch $argc {
+    0 {vlog +incdir+../config/rv32icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
+    1 {vlog +incdir+$1  +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
+}
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+vopt +acc work.testbench -o workopt 
+vsim workopt
+
+view wave
+-- display input and output signals as hexidecimal values
+do ./wave-dos/default-waves.do
+
+-- Run the Simulation 
+#run 5000 
+run -all
+#quit
+noview ../testbench/testbench-imperas.sv
+view wave

wally-pipelined/src/fpu/fcvt.sv

@@ -93,7 +93,7 @@ module fcvt (
 	logic [8:0]	i;
 	always_comb begin
 			i = 0;
-			while (~PosInt[64-1-i] && i <= `XLEN) i = i+1;  // search for leading one 
+			while (~PosInt[64-1-i] && i < `XLEN) i = i+1;  // search for leading one 
 			LZResP = i+1;    // compute shift count
 	end
 

wally-pipelined/src/fpu/fpu.sv

@@ -153,7 +153,7 @@ module fpu (
       flopenrc #(1) DECtrlRegE1(clk, reset, FlushE, ~StallE, FDivStartD, FDivStartE);
       flopenrc #(15) DECtrlRegE2(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, 
                                                             {Adr1E,         Adr2E,         Adr3E});
-      flopenrc #(22) DECtrlReg3(clk, reset, FlushE, ~StallE, 
+      flopenrc #(17) DECtrlReg3(clk, reset, FlushE, ~StallE, 
                            {FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD},
                            {FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE});
 
@@ -242,7 +242,7 @@ module fpu (
       flopenrc #(64) EMRegCvt1(clk, reset, FlushM, ~StallM, CvtResE, CvtResM);
       flopenrc #(5) EMRegCvt2(clk, reset, FlushM, ~StallM, CvtFlgE, CvtFlgM);
       
-      flopenrc #(22) EMCtrlReg(clk, reset, FlushM, ~StallM,
+      flopenrc #(17) EMCtrlReg(clk, reset, FlushM, ~StallM,
                            {FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE},
                            {FRegWriteM, FResultSelM, FResSelM, FIntResSelM, FrmM, FmtM, FOpCtrlM, FWriteIntM});
 
@@ -272,7 +272,7 @@ module fpu (
 
       flopenrc #(64) MWRegClass2(clk, reset, FlushW, ~StallW, FResM, FResW);
       
-      flopenrc #(11) MWCtrlReg(clk, reset, FlushW, ~StallW,
+      flopenrc #(6) MWCtrlReg(clk, reset, FlushW, ~StallW,
                            {FRegWriteM, FResultSelM, FmtM, FWriteIntM},
                            {FRegWriteW, FResultSelW, FmtW, FWriteIntW});
       

wally-pipelined/testbench/testbench-imperas.sv

@@ -57,12 +57,8 @@ module testbench();
 string tests32f[] = '{
     "rv32f/I-FADD-S-01", "2000",
     "rv32f/I-FCLASS-S-01", "2000",
-    "rv32f/I-FCVT-S-L-01", "2000",
-    "rv32f/I-FCVT-S-LU-01", "2000",
     "rv32f/I-FCVT-S-W-01", "2000",
     "rv32f/I-FCVT-S-WU-01", "2000",
-    "rv32f/I-FCVT-L-S-01", "2000",
-    "rv32f/I-FCVT-LU-S-01", "2000",
     "rv32f/I-FCVT-W-S-01", "2000",
     "rv32f/I-FCVT-WU-S-01", "2000",
     // "rv32f/I-FDIV-S-01", "2000",