Added integer inputs and flags to divsqrt

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -44,6 +44,9 @@ module fdivsqrt(
   input  logic StallM,
   input  logic StallE,
   input  logic SqrtE, SqrtM,
+	input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+	input  logic [2:0] 	Funct3E, Funct3M,
+	input  logic MDUE, W64E,
   output logic DivSM,
   output logic DivBusy,
   output logic DivDone,

pipelined/src/fpu/fpu.sv

@@ -36,11 +36,13 @@ module fpu (
    input  logic  [2:0] 	     FRM_REGW,   // Rounding mode (from CSR)
    input  logic  [31:0] 	  InstrD,     // instruction (from IFU)
    input  logic  [`FLEN-1:0] ReadDataW,  // Read data (from LSU)
-  input logic  [`XLEN-1:0] ForwardedSrcAE, // Integer input (from IEU)
+   input  logic  [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input (from IEU)
    input  logic 		        StallE, StallM, StallW, // stall signals (from HZU)
    input  logic 		        FlushE, FlushM, FlushW, // flush signals (from HZU)
    input  logic  [4:0] 	     RdM, RdW,   // which FP register to write to (from IEU)
    input  logic  [1:0]       STATUS_FS,  // Is floating-point enabled? (From privileged unit)
+   input  logic  [2:0] 	     Funct3E, Funct3M,
+	input  logic 		        MDUE, W64E,
    output logic 		        FRegWriteM, // FP register write enable (to privileged unit)
    output logic 		        FpLoadStoreM,  // Fp load instruction? (to LSU)
    output logic 		        FStallD,       // Stall the decode stage (To HZU)
@@ -259,8 +261,11 @@ module fpu (
    // *** add other opperations
    fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
                   .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE,
+                  .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E,
                   .StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal
                   .QmM, .DivDone(DivDoneM));
+
+                  //
    // compare
    //    - fmin/fmax
    //    - flt/fle/feq

pipelined/src/wally/wallypipelinedcore.sv

@@ -393,6 +393,8 @@ module wallypipelinedcore (
          .STATUS_FS, // is floating-point enabled?
          .FRegWriteM, // FP register write enable
          .FpLoadStoreM,
+         .ForwardedSrcBE, // Integer input for intdiv
+         .Funct3E, .Funct3M, .MDUE, .W64E, // Integer flags and functions
          .FStallD, // Stall the decode stage
          .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation
          .FWriteDataM, // Data to be written to memory