From b4d9d2370c805f521ca320f4df928a9dd26c2e64 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 13 Jul 2023 14:10:45 -0500 Subject: [PATCH 1/3] Somehow the Arty A7 device tree was missing. --- linux/devicetree/wally-artya7.dts | 76 +++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 linux/devicetree/wally-artya7.dts diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts new file mode 100644 index 000000000..82e48d70f --- /dev/null +++ b/linux/devicetree/wally-artya7.dts @@ -0,0 +1,76 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "wally-virt"; + model = "wally-virt,qemu"; + + chosen { + linux,initrd-end = <0x85c43a00>; + linux,initrd-start = <0x84200000>; + bootargs = "root=/dev/vda ro"; + stdout-path = "/soc/uart@10000000"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00 0x80000000 0x00 0x08000000>; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + clock-frequency = <0xE4E1C0>; + timebase-frequency = <0xE4E1C0>; + + cpu@0 { + phandle = <0x01>; + device_type = "cpu"; + reg = <0x00>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsu"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x02>; + }; + }; + }; + + soc { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "simple-bus"; + ranges; + + uart@10000000 { + interrupts = <0x0a>; + interrupt-parent = <0x03>; + clock-frequency = <0xE4E1C0>; + reg = <0x00 0x10000000 0x00 0x100>; + compatible = "ns16550a"; + }; + + plic@c000000 { + phandle = <0x03>; + riscv,ndev = <0x35>; + reg = <0x00 0xc000000 0x00 0x210000>; + interrupts-extended = <0x02 0x0b 0x02 0x09>; + interrupt-controller; + compatible = "sifive,plic-1.0.0\0riscv,plic0"; + #interrupt-cells = <0x01>; + #address-cells = <0x00>; + }; + + clint@2000000 { + interrupts-extended = <0x02 0x03 0x02 0x07>; + reg = <0x00 0x2000000 0x00 0x10000>; + compatible = "sifive,clint0\0riscv,clint0"; + }; + }; +}; From 6ddd8d4e2b80cdca401f231995bcfd02e72b1782 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 14 Jul 2023 15:47:05 -0500 Subject: [PATCH 2/3] Fixed the icache and dcache overlogging issue. --- testbench/common/loggers.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 18aa2de34..9dd2a7950 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -138,6 +138,7 @@ module loggers import cvw::*; #(parameter cvw_t P, assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & dut.core.ifu.immu.immu.pmachecker.Cacheable & ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage & + dut.core.ifu.bus.icache.icache.cachefsm.CacheEn & ~reset; flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; @@ -190,6 +191,7 @@ module loggers import cvw::*; #(parameter cvw_t P, assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & + dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn & (AccessTypeString != "NULL"); initial begin From 20751790f67b26256a3314b11b84a42ed6cfdbe1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 14 Jul 2023 16:31:44 -0500 Subject: [PATCH 3/3] Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations. --- src/cache/cachefsm.sv | 3 ++- src/privileged/csrc.sv | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 0909ae82d..58aa9b477 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -92,7 +92,8 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( assign FlushFlag = FlushAdrFlag & FlushWayFlag; // outputs for the performance counters. - assign CacheAccess = (|CacheRW) & CurrState == STATE_READY; // exclusion-tag: icache CacheW + assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) | + (CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW assign CacheMiss = CacheAccess & ~CacheHit; // special case on reset. When the fsm first exists reset the diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index 0ee13d865..2944b1a66 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -101,10 +101,10 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong assign CounterEvent[11] = LoadStallM; // Load Stalls. don't want to suppress on flush as this only happens if flushed. assign CounterEvent[12] = StoreStallM; // Store Stall - assign CounterEvent[13] = DCacheAccess & InstrValidNotFlushedM; // data cache access + assign CounterEvent[13] = DCacheAccess; // data cache access assign CounterEvent[14] = DCacheMiss; // data cache miss. Miss asserted 1 cycle at start of cache miss assign CounterEvent[15] = DCacheStallM; // d cache miss cycles - assign CounterEvent[16] = ICacheAccess & InstrValidNotFlushedM; // instruction cache access + assign CounterEvent[16] = ICacheAccess; // instruction cache access assign CounterEvent[17] = ICacheMiss; // instruction cache miss. Miss asserted 1 cycle at start of cache miss assign CounterEvent[18] = ICacheStallF; // i cache miss cycles assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM; // CSR writes @@ -187,4 +187,4 @@ module csrc import cvw::*; #(parameter cvw_t P) ( end endmodule -// mounteren should only exist if u-mode exists \ No newline at end of file +// mounteren should only exist if u-mode exists