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merge conflict resolved -- Ross and I made the same fix

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bbracker 2021-05-03 10:10:42 -04:00
commit c643372e1d
2 changed files with 65 additions and 64 deletions
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2
wally-pipelined/src/ifu/localHistoryPredictor.sv
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@ -44,7 +44,7 @@ module localHistoryPredictor
); );
logic [2**m-1:0][k-1:0] LHRNextF; logic [2**m-1:0][k-1:0] LHRNextF;
logic [k-1:0] LHRF, LHRFNext, ForwardLHRNext; logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext;
logic [m-1:0] LookUpPCIndex, UpdatePCIndex; logic [m-1:0] LookUpPCIndex, UpdatePCIndex;
logic [1:0] PredictionMemory; logic [1:0] PredictionMemory;
logic DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF; logic DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;

3
wally-pipelined/src/muldiv/div.sv
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@ -282,7 +282,8 @@ module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c,
fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]); fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]);
end end
endgenerate endgenerate
assign carry = {1'b0, carry_temp[WIDTH-1:1], 1'b0}; //assign carry = {1'b0, carry_temp[WIDTH-1:1], 1'b0}; // trmimmed excess bit dh 5/3/21
assign carry = {carry_temp[WIDTH-1:1], 1'b0};
endmodule // adder endmodule // adder