From c61526d034bd8f7ea6b15a2acec4f201332a4d7e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 24 Oct 2023 18:08:33 -0500 Subject: [PATCH] Possible fix for wfi. --- src/hazard/hazard.sv | 16 +++++++++++----- src/privileged/csr.sv | 6 +++++- src/wally/wallypipelinedcore.sv | 2 +- 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 8efa454d9..b47ac410d 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -27,6 +27,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module hazard ( + input logic clk, reset, // Detect hazards input logic BPWrongE, CSRWriteFenceM, RetM, TrapM, input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, @@ -45,10 +46,12 @@ module hazard ( logic FlushDCause, FlushECause, FlushMCause, FlushWCause; logic WFIStallM, WFIInterruptedM; + logic wfiW; // WFI logic - assign WFIStallM = wfiM & ~IntPendingM; // WFI waiting for an interrupt or timeout - assign WFIInterruptedM = wfiM & IntPendingM; // WFI detects a pending interrupt. Retire WFI; trap if interrupt is enabled. + flopenrc #(1) wfiWReg(clk, reset, FlushW, ~StallW, wfiM, wfiW); + assign WFIStallM = wfiW & ~IntPendingM; // WFI waiting for an interrupt or timeout + assign WFIInterruptedM = wfiW & IntPendingM; // WFI detects a pending interrupt. Retire WFI; trap if interrupt is enabled. // stalls and flushes // loads: stall for one cycle if the subsequent instruction depends on the load @@ -73,7 +76,8 @@ module hazard ( assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPWrongE; assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPWrongE & ~(DivBusyE | FDivBusyE)); assign FlushMCause = TrapM | RetM | CSRWriteFenceM; - assign FlushWCause = TrapM & ~WFIInterruptedM; + //assign FlushWCause = TrapM & ~WFIInterruptedM; + assign FlushWCause = TrapM; // Stall causes // Most data depenency stalls are identified in the decode stage @@ -86,11 +90,13 @@ module hazard ( assign StallFCause = '0; assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FPUStallD) & ~FlushDCause; assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; - assign StallMCause = WFIStallM & ~FlushMCause; + //assign StallMCause = WFIStallM & ~FlushMCause; + assign StallMCause = '0; // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1. // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause; // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out. - assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause); + //assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause); + assign StallWCause = (IFUStallF & ~FlushDCause) | ((LSUStallM | WFIStallM) & ~FlushWCause); // Stall each stage for cause or if the next stage is stalled // coverage off: StallFCause is always 0 diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 4cdce4989..38e8945d9 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -200,9 +200,13 @@ module csr import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////// // CSR Write values /////////////////////////////////////////// + logic [P.XLEN-1:0] PCW; // *** can optimize out it's just PCM for all now. + logic wfiW; + flopenr #(P.XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); + flopenrc #(1) wfiWReg(clk, reset, FlushW, ~StallW, wfiM, wfiW); assign CSRAdrM = InstrM[31:20]; - assign UnalignedNextEPCM = TrapM ? ((wfiM & IntPendingM) ? PCM+4 : PCM) : CSRWriteValM; + assign UnalignedNextEPCM = TrapM ? ((wfiW & IntPendingM) ? PCW+4 : PCM) : CSRWriteValM; assign NextEPCM = P.C_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[P.XLEN-1], CSRWriteValM[3:0]}; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 00b348660..5df543903 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -264,7 +264,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( end // global stall and flush control - hazard hzu( + hazard hzu(.clk, .reset, .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM, .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, .LSUStallM, .IFUStallF,