From c60a1fed69e54f92fb404bea9464ece592bc6114 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Mon, 26 Jul 2021 12:22:53 -0500
Subject: [PATCH] Fixed bug which caused stores to take an extra clock cycle.

---
 wally-pipelined/src/cache/dcache.sv | 2 --
 1 file changed, 2 deletions(-)

diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index a3aeb10e5..c5d20b3a2 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -553,7 +553,6 @@ module dcache
 	  DCacheStall = 1'b0;
 	  SRAMWordWriteEnableM = 1'b1;
 	  SetDirtyM = 1'b1;
-	  DCacheStall = 1'b1;
 	  LRUWriteEn = 1'b1;
 	  
 	  if(StallWtoDCache) begin 
@@ -922,7 +921,6 @@ module dcache
 	  DCacheStall = 1'b0;
 	  SRAMWordWriteEnableM = 1'b1;
 	  SetDirtyM = 1'b1;
-	  DCacheStall = 1'b1;
 	  LRUWriteEn = 1'b1;
 	  
 	  if(StallWtoDCache) begin