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Replaced dcache generate ORing with or_rows.

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This commit is contained in:
Ross Thompson 2021-08-25 13:46:36 -05:00
parent e5336f4ee1
commit c5e2443298
2 changed files with 16 additions and 23 deletions
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21
wally-pipelined/src/cache/cacheway.sv vendored
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@ -30,13 +30,12 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
(input logic clk,
input logic reset,
input logic [$clog2(NUMLINES)-1:0] Adr,
input logic [$clog2(NUMLINES)-1:0] RAdr,
input logic [`PA_BITS-1:OFFSETLEN+INDEXLEN] MemPAdrM,
input logic WriteEnable,
input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable,
input logic TagWriteEnable,
input logic [BLOCKLEN-1:0] WriteData,
input logic [TAGLEN-1:0] WriteTag,
input logic SetValid,
input logic ClearValid,
input logic SetDirty,
@ -63,7 +62,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
sram1rw #(.DEPTH(`XLEN),
.WIDTH(NUMLINES))
CacheDataMem(.clk(clk),
.Addr(Adr),
.Addr(RAdr),
.ReadData(ReadDataBlockWayM[(words+1)*`XLEN-1:words*`XLEN]),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words]));
@ -73,9 +72,9 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
sram1rw #(.DEPTH(TAGLEN),
.WIDTH(NUMLINES))
CacheTagMem(.clk(clk),
.Addr(Adr),
.Addr(RAdr),
.ReadData(ReadTag),
.WriteData(WriteTag),
.WriteData(MemPAdrM),
.WriteEnable(TagWriteEnable));
assign WayHit = Valid & (ReadTag == MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
@ -88,17 +87,17 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
always_ff @(posedge clk, posedge reset) begin
if (reset)
ValidBits <= {NUMLINES{1'b0}};
else if (SetValid & WriteEnable) ValidBits[Adr] <= 1'b1;
else if (ClearValid & WriteEnable) ValidBits[Adr] <= 1'b0;
Valid <= ValidBits[Adr];
else if (SetValid & WriteEnable) ValidBits[RAdr] <= 1'b1;
else if (ClearValid & WriteEnable) ValidBits[RAdr] <= 1'b0;
Valid <= ValidBits[RAdr];
end
always_ff @(posedge clk, posedge reset) begin
if (reset)
DirtyBits <= {NUMLINES{1'b0}};
else if (SetDirty & WriteEnable) DirtyBits[Adr] <= 1'b1;
else if (ClearDirty & WriteEnable) DirtyBits[Adr] <= 1'b0;
Dirty <= DirtyBits[Adr];
else if (SetDirty & WriteEnable) DirtyBits[RAdr] <= 1'b1;
else if (ClearDirty & WriteEnable) DirtyBits[RAdr] <= 1'b0;
Dirty <= DirtyBits[RAdr];
end

18
wally-pipelined/src/cache/dcache.sv vendored
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@ -205,13 +205,12 @@ module dcache
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
MemWay[NUMWAYS-1:0](.clk,
.reset,
.Adr(SRAMAdr),
.RAdr(SRAMAdr),
.MemPAdrM(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
.WriteEnable(SRAMWayWriteEnable),
.WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMBlockWayWriteEnableM),
.WriteData(SRAMWriteData),
.WriteTag(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
.SetValid(SetValidM),
.ClearValid(ClearValidM),
.SetDirty(SetDirtyM),
@ -264,22 +263,17 @@ module dcache
// ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways.
// Need to OR together each way in a bitwise manner.
// Final part of the AO Mux.
genvar index;
always_comb begin
ReadDataBlockM = '0;
VictimReadDataBlockM = '0;
VictimTag = '0;
for(int index = 0; index < NUMWAYS; index++) begin
ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM[index];
VictimTag = VictimTag | VictimTagWay[index];
end
end
or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataBlockWayMaskedM), .y(ReadDataBlockM));
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
assign VictimDirty = | VictimDirtyWay;
// Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
// easily build a variable input mux.
// *** consider using a limited range shift to do this final muxing.
genvar index;
generate
for (index = 0; index < WORDSPERLINE; index++) begin
assign ReadDataBlockSetsM[index] = ReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)];