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Update SRAM to /proj/wally

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This commit is contained in:
James Stine 2022-07-08 08:09:55 -05:00
parent 43549b10fb
commit c5dfefe669
2 changed files with 4 additions and 4 deletions
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6
pipelined/src/cache/sram1p1rw.sv vendored
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@ -57,9 +57,9 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
for (index=0; index < WIDTH; index++)
assign BitWriteMask[index] = ByteMask[index/8];
TS1N28HPCPSVTB64X128M4SWBASO sram(
.SLP(1'b0), .SD(1'b0), .CLK(clk), .CEB(1'b0), .WEB(~WriteEnable),
.CEBM(1'b0), .WEBM(1'b0), .AWT(1'b0), .A(Adr), .D(CacheWriteData),
.BWEB(~BitWriteMask), .AM('b0), .DM('b0), .BWEBM('b0), .BIST(1'b0), .Q(ReadData)
.CLK(clk), .CEB(1'b0), .WEB(~WriteEnable),
.A(Adr), .D(CacheWriteData),
.BWEB(~BitWriteMask), .Q(ReadData)
);
end else begin

2
pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v vendored
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@ -1 +1 @@
/home/jstine/memory/ts1n28hpcpsvtb64x128m4swbaso_180a/VERILOG/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v
/proj/wally/memory/ts1n28hpcpsvtb64x128m4sw_180a/VERILOG/ts1n28hpcpsvtb64x128m4sw_180a_tt1v25c.v