Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses

Browse Source
This commit is contained in:
bbracker 2021-11-25 11:01:59 -08:00
parent cb77c1db3a
commit c5d393fbc6
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
wally-pipelined/testbench/testbench-linux.sv
View File

@ -431,12 +431,12 @@ module testbench();
end \ end \
if(`"STAGE`"=="M") begin \ if(`"STAGE`"=="M") begin \
// override on special conditions \ // override on special conditions \
if (ExpectedMemAdrM == 'h10000005) begin \ if (dut.hart.lsu.MemPAdrM == 'h10000005) begin \
//$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); \ //$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \
force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
end \ end \
if(textM.substr(0,5) == "rdtime") begin \ if(textM.substr(0,5) == "rdtime") begin \
//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW); \ $display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \ force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
end \ end \
end \ end \