From 95d64fe4aec950ba364c4ef9bcd6c12325e605b0 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 25 May 2022 17:17:49 -0700 Subject: [PATCH 01/28] idk lol it says this has an unadded change --- pipelined/src/ebu/ahblite.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 35b3797bb..86835d285 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -133,7 +133,8 @@ module ahblite ( 101: 8-beat incrementing burst (INCR8) 110: 16-beat wrapping burst (WRAP16) [wraps if X in 0X000000] 111: 16-beat incrementing burst (INCR16) - */ + *** Remove if not necessary + */ assign HPROT = 4'b0011; // not used; see Section 3.7 From 87cfd62e19aebf84aaa43333aac225f93e7c2402 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 25 May 2022 17:29:45 -0700 Subject: [PATCH 02/28] Added line to testbench to prevent annoying burst sizes --- pipelined/testbench/testbench.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 86760487a..c1587345d 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -374,6 +374,7 @@ module riscvassertions; //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); //assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); + assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); end endmodule From 80965f953c3b2ec32b5bde8e8f290334527ef8e9 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 25 May 2022 18:02:50 -0700 Subject: [PATCH 03/28] added burst size signals to the IFU, EBU, LSU, and busdp --- pipelined/src/ebu/ahblite.sv | 2 ++ pipelined/src/ifu/ifu.sv | 3 ++- pipelined/src/lsu/busdp.sv | 12 +++++++++++- pipelined/src/lsu/lsu.sv | 3 ++- pipelined/src/wally/wallypipelinedcore.sv | 9 ++++++--- 5 files changed, 23 insertions(+), 6 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 86835d285..690d998ac 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -45,6 +45,7 @@ module ahblite ( input logic IFUBusRead, output logic [`XLEN-1:0] IFUBusHRDATA, output logic IFUBusAck, + input logic [2:0] IFUBurstType, // Signals from Data Cache input logic [`PA_BITS-1:0] LSUBusAdr, input logic LSUBusRead, @@ -52,6 +53,7 @@ module ahblite ( input logic [`XLEN-1:0] LSUBusHWDATA, output logic [`XLEN-1:0] LSUBusHRDATA, input logic [2:0] LSUBusSize, + input logic [2:0] LSUBurstType, output logic LSUBusAck, // AHB-Lite external signals (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index be340b2e6..66f4acfdd 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -41,6 +41,7 @@ module ifu ( (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr, (* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUStallF, +(* mark_debug = "true" *) output logic [2:0] IFUBurstType, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Execute output logic [`XLEN-1:0] PCLinkE, @@ -190,7 +191,7 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(.clk, .reset, .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(), - .LSUBusRead(IFUBusRead), .LSUBusSize(), + .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .WordCount(), .DCacheFetchLine(ICacheFetchLine), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index e80de5bde..c64131e31 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -42,7 +42,8 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) input logic LSUBusAck, output logic LSUBusWrite, output logic LSUBusRead, - output logic [2:0] LSUBusSize, + output logic [2:0] LSUBusSize, + output logic [2:0] LSUBurstType, input logic [2:0] LSUFunct3M, output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. output logic [LOGWPL-1:0] WordCount, @@ -67,6 +68,15 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalLSUBusAdr; + always_comb begin + case(WORDSPERLINE) + 4: LSUBurstType = 3'b010; + 8: LSUBurstType = 3'b100; + 16: LSUBurstType = 3'b110; + default: LSUBurstType = 3'b000; + endcase + end + // *** implement flops as an array if feasbile; DCacheBusWriteData might be a problem // *** better name than DCacheBusWriteData genvar index; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index e6458385e..84a92872a 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -69,6 +69,7 @@ module lsu ( (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, (* mark_debug = "true" *) output logic [2:0] LSUBusSize, + (* mark_debug = "true" *) output logic [2:0] LSUBurstType, // page table walker input logic [`XLEN-1:0] SATP_REGW, // from csr input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -211,7 +212,7 @@ module lsu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( .clk, .reset, - .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, + .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index ccbc25df3..21f9dcc58 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -136,6 +136,7 @@ module wallypipelinedcore ( logic [`XLEN-1:0] IFUBusHRDATA; logic IFUBusRead; logic IFUBusAck; + logic [2:0] IFUBurstType; // AHB LSU interface logic [`PA_BITS-1:0] LSUBusAdr; @@ -153,6 +154,7 @@ module wallypipelinedcore ( logic [4:0] InstrClassM; logic InstrAccessFaultF; logic [2:0] LSUBusSize; + logic [2:0] LSUBurstType; logic DCacheMiss; logic DCacheAccess; @@ -168,7 +170,7 @@ module wallypipelinedcore ( .FlushF, .FlushD, .FlushE, .FlushM, // Fetch .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, - .IFUBusRead, .IFUStallF, + .IFUBusRead, .IFUStallF, .IFUBurstType, .ICacheAccess, .ICacheMiss, // Execute @@ -249,7 +251,7 @@ module wallypipelinedcore ( .ReadDataM, .FlushDCacheM, // connected to ahb (all stay the same) .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, - .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, + .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -281,11 +283,12 @@ module wallypipelinedcore ( .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), .IFUBusAdr, - .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, + .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, // Signals from Data Cache .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, .LSUBusHRDATA, .LSUBusSize, + .LSUBurstType, .LSUBusAck, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, From ae460eccd48a2bbac11ab1b02311a5ea184ff8ca Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 26 May 2022 13:35:49 -0700 Subject: [PATCH 04/28] Added signal to monitor HBURST and comments for each burst in busdp --- pipelined/regression/wave-dos/ahb-muldiv.do | 1 + pipelined/src/lsu/busdp.sv | 8 ++++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/pipelined/regression/wave-dos/ahb-muldiv.do b/pipelined/regression/wave-dos/ahb-muldiv.do index 98df30a71..bd212f774 100644 --- a/pipelined/regression/wave-dos/ahb-muldiv.do +++ b/pipelined/regression/wave-dos/ahb-muldiv.do @@ -67,6 +67,7 @@ add wave -hex /testbench/dut/core/ebu/HTRANS add wave -hex /testbench/dut/core/ebu/HRDATA add wave -hex /testbench/dut/core/ebu/HWRITE add wave -hex /testbench/dut/core/ebu/HWDATA +add wave -hex /testbench/dut/core/ebu/HBURST add wave -hex /testbench/dut/core/ebu/CaptureDataM add wave -divider diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index c64131e31..7b837cea1 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -70,10 +70,10 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) always_comb begin case(WORDSPERLINE) - 4: LSUBurstType = 3'b010; - 8: LSUBurstType = 3'b100; - 16: LSUBurstType = 3'b110; - default: LSUBurstType = 3'b000; + 4: LSUBurstType = 3'b010; // WRAP4 + 8: LSUBurstType = 3'b100; // WRAP8 + 16: LSUBurstType = 3'b110; // WRAP16 + default: LSUBurstType = 3'b000; // No Burst endcase end From efce3e4953807e47695f74306c3e36decc8cbcf7 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 26 May 2022 16:29:13 -0700 Subject: [PATCH 05/28] added LSUBurstDone signal to signal when a burst has finished --- pipelined/src/ebu/ahblite.sv | 7 ++++++- pipelined/src/ifu/ifu.sv | 3 ++- pipelined/src/lsu/busdp.sv | 11 ++--------- pipelined/src/lsu/busfsm.sv | 14 ++++++++++++++ pipelined/src/lsu/lsu.sv | 3 ++- pipelined/src/wally/wallypipelinedcore.sv | 9 ++++++--- 6 files changed, 32 insertions(+), 15 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 690d998ac..2c61a1c61 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -46,6 +46,7 @@ module ahblite ( output logic [`XLEN-1:0] IFUBusHRDATA, output logic IFUBusAck, input logic [2:0] IFUBurstType, + input logic IFUBurstDone, // Signals from Data Cache input logic [`PA_BITS-1:0] LSUBusAdr, input logic LSUBusRead, @@ -54,6 +55,7 @@ module ahblite ( output logic [`XLEN-1:0] LSUBusHRDATA, input logic [2:0] LSUBusSize, input logic [2:0] LSUBurstType, + input logic LSUBurstDone, output logic LSUBusAck, // AHB-Lite external signals (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, @@ -89,6 +91,9 @@ module ahblite ( // Data accesses have priority over instructions. However, if a data access comes // while an instruction read is occuring, the instruction read finishes before // the data access can take place. + // *** This is no longer true when adding burst mode. We need to finish the current + // read before doing another read. Need to work this out, but preliminarily we can + // store the current read type in a flop and use that to figure out what burst type to use. flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); @@ -124,7 +129,7 @@ module ahblite ( assign #1 HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; - assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH + assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. 000: Single (SINGLE) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 66f4acfdd..abd4ea2e9 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -42,6 +42,7 @@ module ifu ( (* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic [2:0] IFUBurstType, +(* mark_debug = "true" *) output logic IFUBurstDone, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Execute output logic [`XLEN-1:0] PCLinkE, @@ -191,7 +192,7 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(.clk, .reset, .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(), - .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), + .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUBurstDone(IFUBurstDone), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .WordCount(), .DCacheFetchLine(ICacheFetchLine), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 7b837cea1..f2666cd5d 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -44,6 +44,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic LSUBusRead, output logic [2:0] LSUBusSize, output logic [2:0] LSUBurstType, + output logic LSUBurstDone, input logic [2:0] LSUFunct3M, output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. output logic [LOGWPL-1:0] WordCount, @@ -68,14 +69,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalLSUBusAdr; - always_comb begin - case(WORDSPERLINE) - 4: LSUBurstType = 3'b010; // WRAP4 - 8: LSUBurstType = 3'b100; // WRAP8 - 16: LSUBurstType = 3'b110; // WRAP16 - default: LSUBurstType = 3'b000; // No Burst - endcase - end // *** implement flops as an array if feasbile; DCacheBusWriteData might be a problem // *** better name than DCacheBusWriteData @@ -94,5 +87,5 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, - .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); + .LSUBurstType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index f3860c0d6..cbafdb184 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -48,6 +48,8 @@ module busfsm #(parameter integer WordCountThreshold, output logic LSUBusWrite, output logic LSUBusWriteCrit, output logic LSUBusRead, + output logic [2:0] LSUBurstType, + output logic LSUBurstDone, output logic DCacheBusAck, output logic BusCommittedM, output logic SelUncachedAdr, @@ -62,6 +64,7 @@ module busfsm #(parameter integer WordCountThreshold, logic WordCountFlag; logic [LOGWPL-1:0] NextWordCount; logic UnCachedAccess; + logic [2:0] LocalBurstType; typedef enum logic [2:0] {STATE_BUS_READY, @@ -120,6 +123,17 @@ module busfsm #(parameter integer WordCountThreshold, endcase end + always_comb begin + case(WordCountThreshold) + 4: LSUBurstType = 3'b010; // WRAP4 + 8: LSUBurstType = 3'b100; // WRAP8 + 16: LSUBurstType = 3'b110; // WRAP16 + default: LSUBurstType = 3'b000; // No Burst + endcase // This block might be better in the FSM. WordCountThreshold is WordsPerLine + end + + assign LSUBurstType = (UnCachedAccess) ? LocalBurstType : '0; // Don't want to use burst when doing an Uncached Access + assign LSUBurstDone = WordCountFlag; assign CntReset = BusCurrState == STATE_BUS_READY; assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 84a92872a..3afabe439 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -70,6 +70,7 @@ module lsu ( (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, (* mark_debug = "true" *) output logic [2:0] LSUBusSize, (* mark_debug = "true" *) output logic [2:0] LSUBurstType, + (* mark_debug = "true" *) output logic LSUBurstDone, // page table walker input logic [`XLEN-1:0] SATP_REGW, // from csr input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -212,7 +213,7 @@ module lsu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( .clk, .reset, - .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, + .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUBurstDone, .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 21f9dcc58..557811d34 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -137,6 +137,7 @@ module wallypipelinedcore ( logic IFUBusRead; logic IFUBusAck; logic [2:0] IFUBurstType; + logic IFUBurstDone; // AHB LSU interface logic [`PA_BITS-1:0] LSUBusAdr; @@ -155,6 +156,7 @@ module wallypipelinedcore ( logic InstrAccessFaultF; logic [2:0] LSUBusSize; logic [2:0] LSUBurstType; + logic LSUBurstDone; logic DCacheMiss; logic DCacheAccess; @@ -170,7 +172,7 @@ module wallypipelinedcore ( .FlushF, .FlushD, .FlushE, .FlushM, // Fetch .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, - .IFUBusRead, .IFUStallF, .IFUBurstType, + .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUBurstDone, .ICacheAccess, .ICacheMiss, // Execute @@ -251,7 +253,7 @@ module wallypipelinedcore ( .ReadDataM, .FlushDCacheM, // connected to ahb (all stay the same) .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, - .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, + .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUBurstDone, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -283,12 +285,13 @@ module wallypipelinedcore ( .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), .IFUBusAdr, - .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, + .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, .IFUBurstDone, // Signals from Data Cache .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, .LSUBusHRDATA, .LSUBusSize, .LSUBurstType, + .LSUBurstDone, .LSUBusAck, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, From bddc32ed21119a7741d018311e104d4303823d70 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 26 May 2022 18:41:27 -0700 Subject: [PATCH 06/28] changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word --- pipelined/src/ebu/ahblite.sv | 18 +++++++++--------- pipelined/src/lsu/busfsm.sv | 4 ++-- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 2c61a1c61..b49189a6e 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -111,13 +111,13 @@ module ahblite ( else if (LSUBusWrite)NextBusState = MEMWRITE; else if (IFUBusRead) NextBusState = INSTRREAD; else NextBusState = IDLE; - MEMREAD: if (~HREADY) NextBusState = MEMREAD; - else if (IFUBusRead) NextBusState = INSTRREAD; + MEMREAD: if (~LSUBurstDone) NextBusState = MEMREAD; + else if (IFUBusRead & LSUBurstDone) NextBusState = INSTRREAD; else NextBusState = IDLE; - MEMWRITE: if (~HREADY) NextBusState = MEMWRITE; - else if (IFUBusRead) NextBusState = INSTRREAD; + MEMWRITE: if (~LSUBurstDone) NextBusState = MEMWRITE; + else if (IFUBusRead & LSUBurstDone) NextBusState = INSTRREAD; else NextBusState = IDLE; - INSTRREAD: if (~HREADY) NextBusState = INSTRREAD; + INSTRREAD: if (~IFUBurstDone) NextBusState = INSTRREAD; // *** think about moving to memread/write if LSUBusRead/Write are high else NextBusState = IDLE; // if (IFUBusRead still high) *** need to wait? default: NextBusState = IDLE; endcase @@ -129,7 +129,7 @@ module ahblite ( assign #1 HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; - assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; + assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. 000: Single (SINGLE) @@ -145,7 +145,7 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise + assign HTRANS = [SIGNAL TO SET SEQ] ? 2'b11 : (NextBusState != IDLE) ? 2'b10 : 2'b00; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported assign HWRITE = NextBusState == MEMWRITE; // delay write data by one cycle for @@ -161,7 +161,7 @@ module ahblite ( assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; - assign IFUBusAck = (BusState == INSTRREAD) & (NextBusState != INSTRREAD); - assign LSUBusAck = (BusState == MEMREAD) & (NextBusState != MEMREAD) | (BusState == MEMWRITE) & (NextBusState != MEMWRITE); + assign IFUBusAck = HREADY & (BusState == INSTRREAD); + assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE)); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index cbafdb184..5832fc30d 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -132,8 +132,8 @@ module busfsm #(parameter integer WordCountThreshold, endcase // This block might be better in the FSM. WordCountThreshold is WordsPerLine end - assign LSUBurstType = (UnCachedAccess) ? LocalBurstType : '0; // Don't want to use burst when doing an Uncached Access - assign LSUBurstDone = WordCountFlag; + assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access + assign LSUBurstDone = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; assign CntReset = BusCurrState == STATE_BUS_READY; assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | From f426850bc7b5048526b6c45adff7ce1a43e26623 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sat, 28 May 2022 10:06:26 +0000 Subject: [PATCH 07/28] Reverted incorrect Ack --- pipelined/src/ebu/ahblite.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index b49189a6e..adc3d2639 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -161,7 +161,7 @@ module ahblite ( assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; - assign IFUBusAck = HREADY & (BusState == INSTRREAD); - assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE)); + assign IFUBusAck = (BusState == INSTRREAD) & (NextBusState != INSTRREAD); // *** these are wrong. + assign LSUBusAck = (BusState == MEMREAD) & (NextBusState != MEMREAD) | (BusState == MEMWRITE) & (NextBusState != MEMWRITE); // *** these are wrong. endmodule From c24f88c2e9f0c6fa6d50e914fba3dd4e772e4163 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 31 May 2022 15:57:42 -0700 Subject: [PATCH 08/28] Redid the FSM to prepare for burst mode implementation --- pipelined/src/ebu/ahblite.sv | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index b49189a6e..c2c1fb116 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -111,20 +111,29 @@ module ahblite ( else if (LSUBusWrite)NextBusState = MEMWRITE; else if (IFUBusRead) NextBusState = INSTRREAD; else NextBusState = IDLE; - MEMREAD: if (~LSUBurstDone) NextBusState = MEMREAD; - else if (IFUBusRead & LSUBurstDone) NextBusState = INSTRREAD; - else NextBusState = IDLE; - MEMWRITE: if (~LSUBurstDone) NextBusState = MEMWRITE; - else if (IFUBusRead & LSUBurstDone) NextBusState = INSTRREAD; - else NextBusState = IDLE; - INSTRREAD: if (~IFUBurstDone) NextBusState = INSTRREAD; // *** think about moving to memread/write if LSUBusRead/Write are high - else NextBusState = IDLE; // if (IFUBusRead still high) *** need to wait? + MEMREAD: if (HREADY) NextBusState = MEMREADNEXT; + else NextBusState = MEMREAD; + MEMREADNEXT: if (LSUBurstDone & ~IFUBusRead) NextBusState = IDLE; + else if (LSUBurstDone & IFUBusRead) NextBusState = INSTRREAD; + else NextBusState = MEMREAD; + MEMWRITE: if (HREADY) NextBusState = MEMWRITENEXT; + else NextBusState = MEMWRITE; + MEMWRITENEXT: if (LSUBurstDone & ~IFUBusRead) NextBusState = IDLE; + else if (LSUBurstDone & IFUBusRead) NextBusState = INSTRREAD; + else NextBusState = MEMWRITE; + INSTRREAD: if (HREADY) NextBusState = INSTRREADNEXT; + else NextBusState = INSTRREAD; + INSTRREADNEXT: if (IFUBurstDone & ~LSUBusRead & ~LSUBusWrite) NextBusState = IDLE; + else if (IFUBurstDone & LSUBusRead) NextBusState = MEMREAD; + else if (IFUBurstDone & LSUBusWrite) NextBusState = MEMWRITE; + else NextBusState = INSTRREAD; default: NextBusState = IDLE; endcase // bus outputs - assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); + assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE) | + (NextBusState == MEMREADNEXT) | (NextBusState == MEMWRITENEXT); assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; assign #1 HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway @@ -147,7 +156,7 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 assign HTRANS = [SIGNAL TO SET SEQ] ? 2'b11 : (NextBusState != IDLE) ? 2'b10 : 2'b00; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported - assign HWRITE = NextBusState == MEMWRITE; + assign HWRITE = (NextBusState == MEMWRITE) | (NextBusState == MEMWRITENEXT); // delay write data by one cycle for flop #(`XLEN) wdreg(HCLK, LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes From 56121b3587a572d51d3d0ad2cce54e75196c46f9 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 31 May 2022 16:33:05 -0700 Subject: [PATCH 09/28] Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access --- pipelined/src/ebu/ahblite.sv | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index a4f5713db..6ecedccca 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -75,10 +75,11 @@ module ahblite ( (* mark_debug = "true" *) output logic HWRITED ); - typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype; + typedef enum logic [2:0] {IDLE, MEMREAD, MEMREADNEXT, MEMWRITE, MEMWRITENEXT, INSTRREAD, INSTRREADNEXT} statetype; statetype BusState, NextBusState; logic GrantData; + logic SubsequentAccess; logic [31:0] AccessAddress; logic [2:0] ISize; @@ -135,6 +136,7 @@ module ahblite ( assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE) | (NextBusState == MEMREADNEXT) | (NextBusState == MEMWRITENEXT); assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; + assign #1 SubsequentAccess = (GrantData) ? |(AccessAddress[$clog2(`XLEN):0]) : |(AccessAddress[5:0]); assign #1 HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; @@ -154,7 +156,7 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HTRANS = [SIGNAL TO SET SEQ] ? 2'b11 : (NextBusState != IDLE) ? 2'b10 : 2'b00; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise + assign HTRANS = SubsequentAccess ? 2'b11 : (NextBusState != IDLE) ? 2'b10 : 2'b00; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE) | (NextBusState == MEMWRITENEXT); // delay write data by one cycle for @@ -170,7 +172,7 @@ module ahblite ( assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; - assign IFUBusAck = (BusState == INSTRREAD) & (NextBusState != INSTRREAD); // *** these are wrong. - assign LSUBusAck = (BusState == MEMREAD) & (NextBusState != MEMREAD) | (BusState == MEMWRITE) & (NextBusState != MEMWRITE); // *** these are wrong. + assign IFUBusAck = (BusState == INSTRREADNEXT); + assign LSUBusAck = (BusState == MEMREADNEXT) | (BusState == MEMWRITENEXT); endmodule From 108f32e9df36e00535262f6748e095762f27a89a Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 1 Jun 2022 01:04:49 +0000 Subject: [PATCH 10/28] Fixed double assignment on LSUBurstType --- pipelined/src/lsu/busfsm.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 5832fc30d..c8a0ecf15 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -125,10 +125,10 @@ module busfsm #(parameter integer WordCountThreshold, always_comb begin case(WordCountThreshold) - 4: LSUBurstType = 3'b010; // WRAP4 - 8: LSUBurstType = 3'b100; // WRAP8 - 16: LSUBurstType = 3'b110; // WRAP16 - default: LSUBurstType = 3'b000; // No Burst + 4: LocalBurstType = 3'b010; // WRAP4 + 8: LocalBurstType = 3'b100; // WRAP8 + 16: LocalBurstType = 3'b110; // WRAP16 + default: LocalBurstType = 3'b000; // No Burst endcase // This block might be better in the FSM. WordCountThreshold is WordsPerLine end From 90c5e5d319700a80b7e76d5cb763f5e277467a07 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 7 Jun 2022 11:22:53 +0000 Subject: [PATCH 11/28] Reworked bus to handle burst interfacing --- pipelined/src/ebu/ahblite.sv | 7 +++++- pipelined/src/ebu/todolist | 26 +++++++++++++++++++++++ pipelined/src/ifu/ifu.sv | 3 ++- pipelined/src/lsu/busdp.sv | 4 +++- pipelined/src/lsu/busfsm.sv | 21 ++++++++++++------ pipelined/src/lsu/lsu.sv | 3 ++- pipelined/src/wally/wallypipelinedcore.sv | 9 +++++--- 7 files changed, 60 insertions(+), 13 deletions(-) create mode 100644 pipelined/src/ebu/todolist diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 6ecedccca..1ffa3a1a9 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -46,6 +46,7 @@ module ahblite ( output logic [`XLEN-1:0] IFUBusHRDATA, output logic IFUBusAck, input logic [2:0] IFUBurstType, + input logic [1:0] IFUTransType, input logic IFUBurstDone, // Signals from Data Cache input logic [`PA_BITS-1:0] LSUBusAdr, @@ -55,6 +56,7 @@ module ahblite ( output logic [`XLEN-1:0] LSUBusHRDATA, input logic [2:0] LSUBusSize, input logic [2:0] LSUBurstType, + input logic [1:0] LSUTransType, input logic LSUBurstDone, output logic LSUBusAck, // AHB-Lite external signals @@ -116,17 +118,20 @@ module ahblite ( else NextBusState = MEMREAD; MEMREADNEXT: if (LSUBurstDone & ~IFUBusRead) NextBusState = IDLE; else if (LSUBurstDone & IFUBusRead) NextBusState = INSTRREAD; + else if (HREADY) NextBusState = MEMREADNEXT; else NextBusState = MEMREAD; MEMWRITE: if (HREADY) NextBusState = MEMWRITENEXT; else NextBusState = MEMWRITE; MEMWRITENEXT: if (LSUBurstDone & ~IFUBusRead) NextBusState = IDLE; else if (LSUBurstDone & IFUBusRead) NextBusState = INSTRREAD; + else if (HREADY) NextBusState = MEMWRITENEXT; else NextBusState = MEMWRITE; INSTRREAD: if (HREADY) NextBusState = INSTRREADNEXT; else NextBusState = INSTRREAD; INSTRREADNEXT: if (IFUBurstDone & ~LSUBusRead & ~LSUBusWrite) NextBusState = IDLE; else if (IFUBurstDone & LSUBusRead) NextBusState = MEMREAD; else if (IFUBurstDone & LSUBusWrite) NextBusState = MEMWRITE; + else if (HREADY) NextBusState = INSTRREADNEXT; else NextBusState = INSTRREAD; default: NextBusState = IDLE; endcase @@ -160,7 +165,7 @@ module ahblite ( assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE) | (NextBusState == MEMWRITENEXT); // delay write data by one cycle for - flop #(`XLEN) wdreg(HCLK, LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); diff --git a/pipelined/src/ebu/todolist b/pipelined/src/ebu/todolist new file mode 100644 index 000000000..8fc8ddf25 --- /dev/null +++ b/pipelined/src/ebu/todolist @@ -0,0 +1,26 @@ +1. Decide whether to use ahblite or busdp implements burst. + a. If ahb, move capture register for the line into ahblite. Busdp will need to indicate length of read/write (probably using HBURST signal) *** Ross likes this one. + b. BusDP generates ALL intermediate addresses. Is still responsible for controlling HBURST. *** David likes this one, Ross from an efficiency standpoint too + +2. (Don't) ignore entire CPU and cache and busdp. Focus on making AHBlite that can implement burst and non-burst mode. + a. modify ifu to use burst. immediately detects if its working. + i. make sure we collect the right stuff from memory. (gets captured into ahblite's capture register) + b. modify busdp to use new ahblite interface. + i. remove capture register. + ii. modify fsm to expect one ack, not however many it expects right now + iii. increase width of data coming from ahb to cache line length. + c. modify cache to work with new ahb interface. + i. output full cacheline to ahb + ii. word select multiplexer (subcachelineread + lines before it) will be controlled by word count in ahb. + v. ONLY NEED MUX. + +// Don't do A + + assign CntEn = PreCntEn & LSUBusAck | (DCacheFetchLine | DCacheWriteLine); + assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine); + + Have BusDP output HBURST (Done) and HTRANS (*** TODO) [SEQ/NONSEQ/IDLE] + + Add delayed word count flop for internal capture of HRDATA and pushing HWDATA + WordCount is used to select which word to write. send current to cache. + BusDP handles HWDATA and just pushes it to ahblite.sv \ No newline at end of file diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index abd4ea2e9..37f07f8fd 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -42,6 +42,7 @@ module ifu ( (* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic [2:0] IFUBurstType, +(* mark_debug = "true" *) output logic [1:0] IFUTransType, (* mark_debug = "true" *) output logic IFUBurstDone, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Execute @@ -192,7 +193,7 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(.clk, .reset, .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(), - .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUBurstDone(IFUBurstDone), + .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUBurstDone(IFUBurstDone), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .WordCount(), .DCacheFetchLine(ICacheFetchLine), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index f2666cd5d..b7b1fbbaa 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -44,6 +44,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic LSUBusRead, output logic [2:0] LSUBusSize, output logic [2:0] LSUBurstType, + output logic [1:0] LSUTransType, // For AHBLite output logic LSUBurstDone, input logic [2:0] LSUFunct3M, output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. @@ -68,6 +69,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalLSUBusAdr; + logic [LOGWPL-1:0] WordCountDelayed; // *** implement flops as an array if feasbile; DCacheBusWriteData might be a problem @@ -87,5 +89,5 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, - .LSUBurstType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); + .LSUBurstType, .LSUTransType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index c8a0ecf15..7e47140f6 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -50,10 +50,11 @@ module busfsm #(parameter integer WordCountThreshold, output logic LSUBusRead, output logic [2:0] LSUBurstType, output logic LSUBurstDone, + output logic [1:0] LSUTransType, output logic DCacheBusAck, output logic BusCommittedM, output logic SelUncachedAdr, - output logic [LOGWPL-1:0] WordCount); + output logic [LOGWPL-1:0] WordCount, WordCountDelayed); @@ -84,12 +85,19 @@ module busfsm #(parameter integer WordCountThreshold, .reset(reset | CntReset), .en(CntEn), .d(NextWordCount), - .q(WordCount)); + .q(WordCount)); + + flopenr #(LOGWPL) + WordCountDelayedReg(.clk(clk), + .reset(reset | CntReset), + .en(CntEn), + .d(WordCount), + .q(WordCountDelayed)); assign NextWordCount = WordCount + 1'b1; - assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]); - assign CntEn = PreCntEn & LSUBusAck; + assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); + assign CntEn = PreCntEn & LSUBusAck | (DCacheFetchLine | DCacheWriteLine); assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; @@ -129,13 +137,14 @@ module busfsm #(parameter integer WordCountThreshold, 8: LocalBurstType = 3'b100; // WRAP8 16: LocalBurstType = 3'b110; // WRAP16 default: LocalBurstType = 3'b000; // No Burst - endcase // This block might be better in the FSM. WordCountThreshold is WordsPerLine + endcase // *** This isn't working, ask someone for help. end assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access assign LSUBurstDone = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; + assign LSUTransType = (|WordCount) ? 2'b11 : (LSUBusRead | LSUBusWrite) ? 2'b10 : 2'b00; - assign CntReset = BusCurrState == STATE_BUS_READY; + assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine); assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 3afabe439..e575f9ae6 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -70,6 +70,7 @@ module lsu ( (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, (* mark_debug = "true" *) output logic [2:0] LSUBusSize, (* mark_debug = "true" *) output logic [2:0] LSUBurstType, + (* mark_debug = "true" *) output logic [1:0] LSUTransType, (* mark_debug = "true" *) output logic LSUBurstDone, // page table walker input logic [`XLEN-1:0] SATP_REGW, // from csr @@ -213,7 +214,7 @@ module lsu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( .clk, .reset, - .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUBurstDone, + .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 557811d34..40b0394b2 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -137,6 +137,7 @@ module wallypipelinedcore ( logic IFUBusRead; logic IFUBusAck; logic [2:0] IFUBurstType; + logic [1:0] IFUTransType; logic IFUBurstDone; // AHB LSU interface @@ -156,6 +157,7 @@ module wallypipelinedcore ( logic InstrAccessFaultF; logic [2:0] LSUBusSize; logic [2:0] LSUBurstType; + logic [1:0] LSUTransType; logic LSUBurstDone; logic DCacheMiss; @@ -172,7 +174,7 @@ module wallypipelinedcore ( .FlushF, .FlushD, .FlushE, .FlushM, // Fetch .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, - .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUBurstDone, + .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUBurstDone, .ICacheAccess, .ICacheMiss, // Execute @@ -253,7 +255,7 @@ module wallypipelinedcore ( .ReadDataM, .FlushDCacheM, // connected to ahb (all stay the same) .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, - .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUBurstDone, + .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -285,12 +287,13 @@ module wallypipelinedcore ( .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), .IFUBusAdr, - .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, .IFUBurstDone, + .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, .IFUTransType, .IFUBurstDone, // Signals from Data Cache .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, .LSUBusHRDATA, .LSUBusSize, .LSUBurstType, + .LSUTransType, .LSUBurstDone, .LSUBusAck, From 85801e75db9b71f2d880bc20fdb88e865ff96abd Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 7 Jun 2022 19:36:39 +0000 Subject: [PATCH 12/28] Fixed off-by-one error in busdp capture --- pipelined/src/lsu/busdp.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index b7b1fbbaa..5ceb3fe3d 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -77,7 +77,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) genvar index; for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer logic [WORDSPERLINE-1:0] CaptureWord; - assign CaptureWord[index] = LSUBusAck & LSUBusRead & (index == WordCount); + assign CaptureWord[index] = LSUBusAck & LSUBusRead & (index == WordCountDelayed); flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(LSUBusHRDATA), .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN])); end From 1d22fc707ad4a278ac83e7301f9ab5d6738b22ca Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 8 Jun 2022 02:19:21 +0000 Subject: [PATCH 13/28] Added lock signal to ensure AHB speaks with the right bus --- pipelined/src/ebu/ahblite.sv | 18 +++++++++++------- pipelined/src/ifu/ifu.sv | 3 ++- pipelined/src/lsu/busdp.sv | 3 ++- pipelined/src/lsu/busfsm.sv | 13 +++++++------ pipelined/src/lsu/lsu.sv | 3 ++- pipelined/src/wally/wallypipelinedcore.sv | 18 ++++++++++++------ 6 files changed, 36 insertions(+), 22 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 1ffa3a1a9..a1a05abc1 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -45,6 +45,7 @@ module ahblite ( input logic IFUBusRead, output logic [`XLEN-1:0] IFUBusHRDATA, output logic IFUBusAck, + output logic IFUBusLock, input logic [2:0] IFUBurstType, input logic [1:0] IFUTransType, input logic IFUBurstDone, @@ -59,6 +60,7 @@ module ahblite ( input logic [1:0] LSUTransType, input logic LSUBurstDone, output logic LSUBusAck, + output logic LSUBusLock, // AHB-Lite external signals (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, (* mark_debug = "true" *) input logic HREADY, HRESP, @@ -116,21 +118,21 @@ module ahblite ( else NextBusState = IDLE; MEMREAD: if (HREADY) NextBusState = MEMREADNEXT; else NextBusState = MEMREAD; - MEMREADNEXT: if (LSUBurstDone & ~IFUBusRead) NextBusState = IDLE; - else if (LSUBurstDone & IFUBusRead) NextBusState = INSTRREAD; + MEMREADNEXT: if (LSUBurstDone & ~(IFUBusRead & ~HREADY)) NextBusState = IDLE; + else if (LSUBurstDone & IFUBusRead & HREADY) NextBusState = INSTRREAD; else if (HREADY) NextBusState = MEMREADNEXT; else NextBusState = MEMREAD; MEMWRITE: if (HREADY) NextBusState = MEMWRITENEXT; else NextBusState = MEMWRITE; - MEMWRITENEXT: if (LSUBurstDone & ~IFUBusRead) NextBusState = IDLE; - else if (LSUBurstDone & IFUBusRead) NextBusState = INSTRREAD; + MEMWRITENEXT: if (LSUBurstDone & ~(IFUBusRead & ~HREADY)) NextBusState = IDLE; + else if (LSUBurstDone & IFUBusRead & HREADY) NextBusState = INSTRREAD; else if (HREADY) NextBusState = MEMWRITENEXT; else NextBusState = MEMWRITE; INSTRREAD: if (HREADY) NextBusState = INSTRREADNEXT; else NextBusState = INSTRREAD; INSTRREADNEXT: if (IFUBurstDone & ~LSUBusRead & ~LSUBusWrite) NextBusState = IDLE; - else if (IFUBurstDone & LSUBusRead) NextBusState = MEMREAD; - else if (IFUBurstDone & LSUBusWrite) NextBusState = MEMWRITE; + else if (IFUBurstDone & LSUBusRead & HREADY) NextBusState = MEMREAD; + else if (IFUBurstDone & LSUBusWrite & HREADY) NextBusState = MEMWRITE; else if (HREADY) NextBusState = INSTRREADNEXT; else NextBusState = INSTRREAD; default: NextBusState = IDLE; @@ -161,7 +163,7 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HTRANS = SubsequentAccess ? 2'b11 : (NextBusState != IDLE) ? 2'b10 : 2'b00; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise + assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE) | (NextBusState == MEMWRITENEXT); // delay write data by one cycle for @@ -177,6 +179,8 @@ module ahblite ( assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; + assign IFUBusLock = (NextBusState == INSTRREAD) | (NextBusState == INSTRREADNEXT); + assign LSUBusLock = (NextBusState == MEMWRITENEXT) | (NextBusState == MEMREADNEXT) | (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); assign IFUBusAck = (BusState == INSTRREADNEXT); assign LSUBusAck = (BusState == MEMREADNEXT) | (BusState == MEMWRITENEXT); diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 37f07f8fd..93c0dc9a3 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -38,6 +38,7 @@ module ifu ( // Bus interface (* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA, (* mark_debug = "true" *) input logic IFUBusAck, +(* mark_debug = "true" *) input logic IFUBusLock, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr, (* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUStallF, @@ -192,7 +193,7 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(.clk, .reset, - .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(), + .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusLock(IFUBusLock), .LSUBusWrite(), .LSUBusWriteCrit(), .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUBurstDone(IFUBurstDone), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .WordCount(), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 5ceb3fe3d..a2e7a8d4d 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -40,6 +40,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) // bus interface input logic [`XLEN-1:0] LSUBusHRDATA, input logic LSUBusAck, + input logic LSUBusLock, output logic LSUBusWrite, output logic LSUBusRead, output logic [2:0] LSUBusSize, @@ -88,6 +89,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, - .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, + .LSUBusAck, .LSUBusLock, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, .LSUBurstType, .LSUTransType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 7e47140f6..1fbaedd57 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -41,6 +41,7 @@ module busfsm #(parameter integer WordCountThreshold, input logic DCacheFetchLine, input logic DCacheWriteLine, input logic LSUBusAck, + input logic LSUBusLock, input logic CPUBusy, input logic CacheableM, @@ -97,7 +98,7 @@ module busfsm #(parameter integer WordCountThreshold, assign NextWordCount = WordCount + 1'b1; assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); - assign CntEn = PreCntEn & LSUBusAck | (DCacheFetchLine | DCacheWriteLine); + assign CntEn = PreCntEn & LSUBusAck | ((DCacheFetchLine | DCacheWriteLine) & LSUBusLock); assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; @@ -133,16 +134,16 @@ module busfsm #(parameter integer WordCountThreshold, always_comb begin case(WordCountThreshold) - 4: LocalBurstType = 3'b010; // WRAP4 - 8: LocalBurstType = 3'b100; // WRAP8 - 16: LocalBurstType = 3'b110; // WRAP16 + 3: LocalBurstType = 3'b011; // INCR4 + 7: LocalBurstType = 3'b101; // INCR8 + 15: LocalBurstType = 3'b111; // INCR16 default: LocalBurstType = 3'b000; // No Burst - endcase // *** This isn't working, ask someone for help. + endcase end assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access assign LSUBurstDone = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; - assign LSUTransType = (|WordCount) ? 2'b11 : (LSUBusRead | LSUBusWrite) ? 2'b10 : 2'b00; + assign LSUTransType = (|WordCount | |WordCountDelayed) ? 2'b11 : (LSUBusRead | LSUBusWrite) ? 2'b10 : 2'b00; assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine); assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index e575f9ae6..ba7287a39 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -66,6 +66,7 @@ module lsu ( (* mark_debug = "true" *) output logic LSUBusRead, (* mark_debug = "true" *) output logic LSUBusWrite, (* mark_debug = "true" *) input logic LSUBusAck, + (* mark_debug = "true" *) input logic LSUBusLock, (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, (* mark_debug = "true" *) output logic [2:0] LSUBusSize, @@ -214,7 +215,7 @@ module lsu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( .clk, .reset, - .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, + .LSUBusHRDATA, .LSUBusAck, .LSUBusLock, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 40b0394b2..fcf849b02 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -135,7 +135,7 @@ module wallypipelinedcore ( logic [`PA_BITS-1:0] IFUBusAdr; logic [`XLEN-1:0] IFUBusHRDATA; logic IFUBusRead; - logic IFUBusAck; + logic IFUBusAck, IFUBusLock; logic [2:0] IFUBurstType; logic [1:0] IFUTransType; logic IFUBurstDone; @@ -144,7 +144,7 @@ module wallypipelinedcore ( logic [`PA_BITS-1:0] LSUBusAdr; logic LSUBusRead; logic LSUBusWrite; - logic LSUBusAck; + logic LSUBusAck, LSUBusLock; logic [`XLEN-1:0] LSUBusHRDATA; logic [`XLEN-1:0] LSUBusHWDATA; @@ -173,7 +173,7 @@ module wallypipelinedcore ( .StallF, .StallD, .StallE, .StallM, .FlushF, .FlushD, .FlushE, .FlushM, // Fetch - .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, + .IFUBusHRDATA, .IFUBusAck, .IFUBusLock, .PCF, .IFUBusAdr, .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUBurstDone, .ICacheAccess, .ICacheMiss, @@ -254,7 +254,7 @@ module wallypipelinedcore ( .IEUAdrE, .IEUAdrM, .WriteDataE, .ReadDataM, .FlushDCacheM, // connected to ahb (all stay the same) - .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, + .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusLock, .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, // connect to csr or privilege and stay the same. @@ -286,8 +286,13 @@ module wallypipelinedcore ( ahblite ebu(// IFU connections .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), - .IFUBusAdr, - .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, .IFUTransType, .IFUBurstDone, + .IFUBusAdr, .IFUBusRead, + .IFUBusHRDATA, + .IFUBurstType, + .IFUTransType, + .IFUBurstDone, + .IFUBusAck, + .IFUBusLock, // Signals from Data Cache .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, .LSUBusHRDATA, @@ -296,6 +301,7 @@ module wallypipelinedcore ( .LSUTransType, .LSUBurstDone, .LSUBusAck, + .LSUBusLock, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, From be658d393319da81d8cc463f1aac29a31b9fb422 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 8 Jun 2022 15:03:15 -0700 Subject: [PATCH 14/28] Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors --- pipelined/src/ebu/ahblite.sv | 64 +++++++++-------------- pipelined/src/ifu/ifu.sv | 8 +-- pipelined/src/lsu/busdp.sv | 8 +-- pipelined/src/lsu/busfsm.sv | 15 +++--- pipelined/src/lsu/lsu.sv | 6 +-- pipelined/src/wally/wallypipelinedcore.sv | 24 ++++----- 6 files changed, 57 insertions(+), 68 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index a1a05abc1..a62a6efee 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -45,10 +45,10 @@ module ahblite ( input logic IFUBusRead, output logic [`XLEN-1:0] IFUBusHRDATA, output logic IFUBusAck, - output logic IFUBusLock, + output logic IFUBusInit, input logic [2:0] IFUBurstType, input logic [1:0] IFUTransType, - input logic IFUBurstDone, + input logic IFUTransComplete, // Signals from Data Cache input logic [`PA_BITS-1:0] LSUBusAdr, input logic LSUBusRead, @@ -58,9 +58,9 @@ module ahblite ( input logic [2:0] LSUBusSize, input logic [2:0] LSUBurstType, input logic [1:0] LSUTransType, - input logic LSUBurstDone, + input logic LSUTransComplete, output logic LSUBusAck, - output logic LSUBusLock, + output logic LSUBusInit, // AHB-Lite external signals (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, (* mark_debug = "true" *) input logic HREADY, HRESP, @@ -79,11 +79,10 @@ module ahblite ( (* mark_debug = "true" *) output logic HWRITED ); - typedef enum logic [2:0] {IDLE, MEMREAD, MEMREADNEXT, MEMWRITE, MEMWRITENEXT, INSTRREAD, INSTRREADNEXT} statetype; + typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype; statetype BusState, NextBusState; logic GrantData; - logic SubsequentAccess; logic [31:0] AccessAddress; logic [2:0] ISize; @@ -112,38 +111,27 @@ module ahblite ( // interface that might be used in place of the ahblite. always_comb case (BusState) - IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions - else if (LSUBusWrite)NextBusState = MEMWRITE; - else if (IFUBusRead) NextBusState = INSTRREAD; - else NextBusState = IDLE; - MEMREAD: if (HREADY) NextBusState = MEMREADNEXT; - else NextBusState = MEMREAD; - MEMREADNEXT: if (LSUBurstDone & ~(IFUBusRead & ~HREADY)) NextBusState = IDLE; - else if (LSUBurstDone & IFUBusRead & HREADY) NextBusState = INSTRREAD; - else if (HREADY) NextBusState = MEMREADNEXT; - else NextBusState = MEMREAD; - MEMWRITE: if (HREADY) NextBusState = MEMWRITENEXT; - else NextBusState = MEMWRITE; - MEMWRITENEXT: if (LSUBurstDone & ~(IFUBusRead & ~HREADY)) NextBusState = IDLE; - else if (LSUBurstDone & IFUBusRead & HREADY) NextBusState = INSTRREAD; - else if (HREADY) NextBusState = MEMWRITENEXT; - else NextBusState = MEMWRITE; - INSTRREAD: if (HREADY) NextBusState = INSTRREADNEXT; - else NextBusState = INSTRREAD; - INSTRREADNEXT: if (IFUBurstDone & ~LSUBusRead & ~LSUBusWrite) NextBusState = IDLE; - else if (IFUBurstDone & LSUBusRead & HREADY) NextBusState = MEMREAD; - else if (IFUBurstDone & LSUBusWrite & HREADY) NextBusState = MEMWRITE; - else if (HREADY) NextBusState = INSTRREADNEXT; - else NextBusState = INSTRREAD; - default: NextBusState = IDLE; + IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions + else if (LSUBusWrite) NextBusState = MEMWRITE; + else if (IFUBusRead) NextBusState = INSTRREAD; + else NextBusState = IDLE; + MEMREAD: if (LSUTransComplete & ~IFUBusRead) NextBusState = INSTRREAD; + else if (LSUTransComplete) NextBusState = IDLE; + else NextBusState = MEMREAD; + MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; + else if (LSUTransComplete) NextBusState = IDLE; + else NextBusState = MEMWRITE; + INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD; + else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE; + else if (IFUTransComplete) NextBusState = IDLE; + else NextBusState = INSTRREAD; + default: NextBusState = IDLE; endcase // bus outputs - assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE) | - (NextBusState == MEMREADNEXT) | (NextBusState == MEMWRITENEXT); + assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; - assign #1 SubsequentAccess = (GrantData) ? |(AccessAddress[$clog2(`XLEN):0]) : |(AccessAddress[5:0]); assign #1 HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; @@ -165,7 +153,7 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported - assign HWRITE = (NextBusState == MEMWRITE) | (NextBusState == MEMWRITENEXT); + assign HWRITE = (NextBusState == MEMWRITE); // delay write data by one cycle for flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes @@ -179,9 +167,9 @@ module ahblite ( assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; - assign IFUBusLock = (NextBusState == INSTRREAD) | (NextBusState == INSTRREADNEXT); - assign LSUBusLock = (NextBusState == MEMWRITENEXT) | (NextBusState == MEMREADNEXT) | (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); - assign IFUBusAck = (BusState == INSTRREADNEXT); - assign LSUBusAck = (BusState == MEMREADNEXT) | (BusState == MEMWRITENEXT); + assign IFUBusInit = (NextBusState == INSTRREAD); + assign LSUBusInit = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); + assign IFUBusAck = HREADY & (BusState == INSTRREAD); + assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE)); endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index cb7f62b89..29d07cc2c 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -38,13 +38,13 @@ module ifu ( // Bus interface (* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA, (* mark_debug = "true" *) input logic IFUBusAck, -(* mark_debug = "true" *) input logic IFUBusLock, +(* mark_debug = "true" *) input logic IFUBusInit, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr, (* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic [2:0] IFUBurstType, (* mark_debug = "true" *) output logic [1:0] IFUTransType, -(* mark_debug = "true" *) output logic IFUBurstDone, +(* mark_debug = "true" *) output logic IFUTransComplete, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Execute output logic [`XLEN-1:0] PCLinkE, @@ -205,8 +205,8 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(.clk, .reset, - .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusLock(IFUBusLock), .LSUBusWrite(), .LSUBusWriteCrit(), - .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUBurstDone(IFUBurstDone), + .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .LSUBusWriteCrit(), + .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .WordCount(), .DCacheFetchLine(ICacheFetchLine), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index a2e7a8d4d..5139efdc1 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -40,13 +40,13 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) // bus interface input logic [`XLEN-1:0] LSUBusHRDATA, input logic LSUBusAck, - input logic LSUBusLock, + input logic LSUBusInit, output logic LSUBusWrite, output logic LSUBusRead, output logic [2:0] LSUBusSize, output logic [2:0] LSUBurstType, output logic [1:0] LSUTransType, // For AHBLite - output logic LSUBurstDone, + output logic LSUTransComplete, input logic [2:0] LSUFunct3M, output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. output logic [LOGWPL-1:0] WordCount, @@ -89,6 +89,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, - .LSUBusAck, .LSUBusLock, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, - .LSUBurstType, .LSUTransType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); + .LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, + .LSUBurstType, .LSUTransType, .LSUTransComplete, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 1fbaedd57..52db7f96e 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -41,7 +41,7 @@ module busfsm #(parameter integer WordCountThreshold, input logic DCacheFetchLine, input logic DCacheWriteLine, input logic LSUBusAck, - input logic LSUBusLock, + input logic LSUBusInit, input logic CPUBusy, input logic CacheableM, @@ -50,7 +50,7 @@ module busfsm #(parameter integer WordCountThreshold, output logic LSUBusWriteCrit, output logic LSUBusRead, output logic [2:0] LSUBurstType, - output logic LSUBurstDone, + output logic LSUTransComplete, output logic [1:0] LSUTransType, output logic DCacheBusAck, output logic BusCommittedM, @@ -98,7 +98,7 @@ module busfsm #(parameter integer WordCountThreshold, assign NextWordCount = WordCount + 1'b1; assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); - assign CntEn = PreCntEn & LSUBusAck | ((DCacheFetchLine | DCacheWriteLine) & LSUBusLock); + assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag; assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; @@ -134,16 +134,17 @@ module busfsm #(parameter integer WordCountThreshold, always_comb begin case(WordCountThreshold) + 1: LocalBurstType = 3'b000; 3: LocalBurstType = 3'b011; // INCR4 7: LocalBurstType = 3'b101; // INCR8 15: LocalBurstType = 3'b111; // INCR16 - default: LocalBurstType = 3'b000; // No Burst + default: LocalBurstType = 3'b001; // No Burst endcase end - assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access - assign LSUBurstDone = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; - assign LSUTransType = (|WordCount | |WordCountDelayed) ? 2'b11 : (LSUBusRead | LSUBusWrite) ? 2'b10 : 2'b00; + assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access. + assign LSUTransComplete = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; + assign LSUTransType = (|WordCount) & ~UncachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & ~WordCountFlag ? 2'b10 : 2'b00; assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine); assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 2788d6231..dbd043d76 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -66,13 +66,13 @@ module lsu ( (* mark_debug = "true" *) output logic LSUBusRead, (* mark_debug = "true" *) output logic LSUBusWrite, (* mark_debug = "true" *) input logic LSUBusAck, - (* mark_debug = "true" *) input logic LSUBusLock, + (* mark_debug = "true" *) input logic LSUBusInit, (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, (* mark_debug = "true" *) output logic [2:0] LSUBusSize, (* mark_debug = "true" *) output logic [2:0] LSUBurstType, (* mark_debug = "true" *) output logic [1:0] LSUTransType, - (* mark_debug = "true" *) output logic LSUBurstDone, + (* mark_debug = "true" *) output logic LSUTransComplete, // page table walker input logic [`XLEN-1:0] SATP_REGW, // from csr input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -215,7 +215,7 @@ module lsu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( .clk, .reset, - .LSUBusHRDATA, .LSUBusAck, .LSUBusLock, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, + .LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index d4a27952b..e1040ee7a 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -134,16 +134,16 @@ module wallypipelinedcore ( logic [`PA_BITS-1:0] IFUBusAdr; logic [`XLEN-1:0] IFUBusHRDATA; logic IFUBusRead; - logic IFUBusAck, IFUBusLock; + logic IFUBusAck, IFUBusInit; logic [2:0] IFUBurstType; logic [1:0] IFUTransType; - logic IFUBurstDone; + logic IFUTransComplete; // AHB LSU interface logic [`PA_BITS-1:0] LSUBusAdr; logic LSUBusRead; logic LSUBusWrite; - logic LSUBusAck, LSUBusLock; + logic LSUBusAck, LSUBusInit; logic [`XLEN-1:0] LSUBusHRDATA; logic [`XLEN-1:0] LSUBusHWDATA; @@ -157,7 +157,7 @@ module wallypipelinedcore ( logic [2:0] LSUBusSize; logic [2:0] LSUBurstType; logic [1:0] LSUTransType; - logic LSUBurstDone; + logic LSUTransComplete; logic DCacheMiss; logic DCacheAccess; @@ -172,8 +172,8 @@ module wallypipelinedcore ( .StallF, .StallD, .StallE, .StallM, .FlushF, .FlushD, .FlushE, .FlushM, // Fetch - .IFUBusHRDATA, .IFUBusAck, .IFUBusLock, .PCF, .IFUBusAdr, - .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUBurstDone, + .IFUBusHRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUBusAdr, + .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUTransComplete, .ICacheAccess, .ICacheMiss, // Execute @@ -253,8 +253,8 @@ module wallypipelinedcore ( .IEUAdrE, .IEUAdrM, .WriteDataE, .ReadDataM, .FlushDCacheM, // connected to ahb (all stay the same) - .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusLock, - .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, + .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, + .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -289,18 +289,18 @@ module wallypipelinedcore ( .IFUBusHRDATA, .IFUBurstType, .IFUTransType, - .IFUBurstDone, + .IFUTransComplete, .IFUBusAck, - .IFUBusLock, + .IFUBusInit, // Signals from Data Cache .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, .LSUBusHRDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, - .LSUBurstDone, + .LSUTransComplete, .LSUBusAck, - .LSUBusLock, + .LSUBusInit, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, From dd33f2a009cdf9c2204d05fd0ba90e3635bdf17b Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 8 Jun 2022 15:29:32 -0700 Subject: [PATCH 15/28] Working version: Fixed error where Word count would always increment even without AHB to bus ACK --- pipelined/src/ebu/ahblite.sv | 4 ++-- pipelined/src/lsu/busfsm.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index a62a6efee..f98779e00 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -167,8 +167,8 @@ module ahblite ( assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; - assign IFUBusInit = (NextBusState == INSTRREAD); - assign LSUBusInit = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); + assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD); + assign LSUBusInit = ((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState == IDLE) & (NextBusState == MEMWRITE); assign IFUBusAck = HREADY & (BusState == INSTRREAD); assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE)); diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 52db7f96e..f2527b7a1 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -144,7 +144,7 @@ module busfsm #(parameter integer WordCountThreshold, assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access. assign LSUTransComplete = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; - assign LSUTransType = (|WordCount) & ~UncachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & ~WordCountFlag ? 2'b10 : 2'b00; + assign LSUTransType = (|WordCount) & ~UnCachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & ~WordCountFlag ? 2'b10 : 2'b00; assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine); assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | From a64e65e54ca9299152b772e23d18edcfbb33f950 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 8 Jun 2022 15:30:32 -0700 Subject: [PATCH 16/28] Fixed ifu displaying LSU bus state in wave.do --- pipelined/regression/wave.do | 3 ++- pipelined/src/ebu/todolist | 26 -------------------------- 2 files changed, 2 insertions(+), 27 deletions(-) delete mode 100644 pipelined/src/ebu/todolist diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index ab6cbc46a..ba1a89e5f 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -468,11 +468,12 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM -add wave -noupdate -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState +add wave -noupdate -group ifu -color Gold /testbench/dut/core/ifu/bus/busdp/busfsm/BusCurrState add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAck add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusHRDATA +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUTransComplete add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0 diff --git a/pipelined/src/ebu/todolist b/pipelined/src/ebu/todolist deleted file mode 100644 index 8fc8ddf25..000000000 --- a/pipelined/src/ebu/todolist +++ /dev/null @@ -1,26 +0,0 @@ -1. Decide whether to use ahblite or busdp implements burst. - a. If ahb, move capture register for the line into ahblite. Busdp will need to indicate length of read/write (probably using HBURST signal) *** Ross likes this one. - b. BusDP generates ALL intermediate addresses. Is still responsible for controlling HBURST. *** David likes this one, Ross from an efficiency standpoint too - -2. (Don't) ignore entire CPU and cache and busdp. Focus on making AHBlite that can implement burst and non-burst mode. - a. modify ifu to use burst. immediately detects if its working. - i. make sure we collect the right stuff from memory. (gets captured into ahblite's capture register) - b. modify busdp to use new ahblite interface. - i. remove capture register. - ii. modify fsm to expect one ack, not however many it expects right now - iii. increase width of data coming from ahb to cache line length. - c. modify cache to work with new ahb interface. - i. output full cacheline to ahb - ii. word select multiplexer (subcachelineread + lines before it) will be controlled by word count in ahb. - v. ONLY NEED MUX. - -// Don't do A - - assign CntEn = PreCntEn & LSUBusAck | (DCacheFetchLine | DCacheWriteLine); - assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine); - - Have BusDP output HBURST (Done) and HTRANS (*** TODO) [SEQ/NONSEQ/IDLE] - - Add delayed word count flop for internal capture of HRDATA and pushing HWDATA - WordCount is used to select which word to write. send current to cache. - BusDP handles HWDATA and just pushes it to ahblite.sv \ No newline at end of file From 655266a216c5efe3ca305a6d6c415e6734099c39 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 8 Jun 2022 15:59:15 -0700 Subject: [PATCH 17/28] Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending --- pipelined/src/ebu/ahblite.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index f98779e00..4cfad7bb8 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -115,7 +115,7 @@ module ahblite ( else if (LSUBusWrite) NextBusState = MEMWRITE; else if (IFUBusRead) NextBusState = INSTRREAD; else NextBusState = IDLE; - MEMREAD: if (LSUTransComplete & ~IFUBusRead) NextBusState = INSTRREAD; + MEMREAD: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; else if (LSUTransComplete) NextBusState = IDLE; else NextBusState = MEMREAD; MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; From 1605544bfc9711600299cddd916d090c400a2326 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 8 Jun 2022 17:34:02 -0700 Subject: [PATCH 18/28] Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request. --- pipelined/src/ebu/ahblite.sv | 2 +- pipelined/src/lsu/busfsm.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 4cfad7bb8..e4cc5edfd 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -155,7 +155,7 @@ module ahblite ( assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE); // delay write data by one cycle for - flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck | IFUBusInit | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index f2527b7a1..984c2c02a 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -146,7 +146,7 @@ module busfsm #(parameter integer WordCountThreshold, assign LSUTransComplete = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; assign LSUTransType = (|WordCount) & ~UnCachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & ~WordCountFlag ? 2'b10 : 2'b00; - assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine); + assign CntReset = (BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine)) | LSUTransComplete; assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | From 8ae57f075fee81ff05f4a34ce4d5f569bff55470 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 8 Jun 2022 18:58:07 -0700 Subject: [PATCH 19/28] Fixed error when doing uncached accesses where HTRANS was always 2 --- pipelined/src/lsu/busfsm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 984c2c02a..37da283d2 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -144,7 +144,7 @@ module busfsm #(parameter integer WordCountThreshold, assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access. assign LSUTransComplete = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; - assign LSUTransType = (|WordCount) & ~UnCachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & ~WordCountFlag ? 2'b10 : 2'b00; + assign LSUTransType = (|WordCount) & ~UnCachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag | UnCachedAccess) ? 2'b10 : 2'b00; assign CntReset = (BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine)) | LSUTransComplete; assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | From c4bc6082687889be71a9dc980810667b47689679 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 9 Jun 2022 17:33:51 -0700 Subject: [PATCH 20/28] Changes made on 9th Jun --- pipelined/src/ebu/ahblite.sv | 10 +++++----- pipelined/src/lsu/busdp.sv | 2 +- pipelined/src/lsu/busfsm.sv | 16 +++++++++------- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index e4cc5edfd..68561cbac 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -115,11 +115,11 @@ module ahblite ( else if (LSUBusWrite) NextBusState = MEMWRITE; else if (IFUBusRead) NextBusState = INSTRREAD; else NextBusState = IDLE; - MEMREAD: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; + MEMREAD: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; else if (LSUTransComplete) NextBusState = IDLE; else NextBusState = MEMREAD; MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; - else if (LSUTransComplete) NextBusState = IDLE; + else if (LSUTransComplete) NextBusState = IDLE;// Ram cannot handle a read after a write, Do not send one. else NextBusState = MEMWRITE; INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD; else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE; @@ -155,7 +155,7 @@ module ahblite ( assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE); // delay write data by one cycle for - flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck | IFUBusInit | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); @@ -167,8 +167,8 @@ module ahblite ( assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; - assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD); - assign LSUBusInit = ((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState == IDLE) & (NextBusState == MEMWRITE); + assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD) & HREADY; + assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState == IDLE) & (NextBusState == MEMWRITE)) & HREADY; assign IFUBusAck = HREADY & (BusState == INSTRREAD); assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE)); diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 5139efdc1..f1156b446 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -68,7 +68,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic BusStall, output logic BusCommittedM); - localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; + localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 1; logic [`PA_BITS-1:0] LocalLSUBusAdr; logic [LOGWPL-1:0] WordCountDelayed; diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 37da283d2..2285591cb 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -65,7 +65,7 @@ module busfsm #(parameter integer WordCountThreshold, logic CntReset; logic WordCountFlag; logic [LOGWPL-1:0] NextWordCount; - logic UnCachedAccess; + logic UnCachedAccess, UnCachedRW; logic [2:0] LocalBurstType; @@ -97,6 +97,7 @@ module busfsm #(parameter integer WordCountThreshold, assign NextWordCount = WordCount + 1'b1; + assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag; @@ -138,21 +139,20 @@ module busfsm #(parameter integer WordCountThreshold, 3: LocalBurstType = 3'b011; // INCR4 7: LocalBurstType = 3'b101; // INCR8 15: LocalBurstType = 3'b111; // INCR16 - default: LocalBurstType = 3'b001; // No Burst + default: LocalBurstType = 3'b001; // INCR without end. endcase end - assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access. - assign LSUTransComplete = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; - assign LSUTransType = (|WordCount) & ~UnCachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag | UnCachedAccess) ? 2'b10 : 2'b00; + assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. + assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck; + assign LSUTransType = (|WordCount) & ~UnCachedRW ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag) ? 2'b10 : 2'b00; - assign CntReset = (BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine)) | LSUTransComplete; + assign CntReset = BusCurrState == STATE_BUS_READY; assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); - assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE); @@ -164,6 +164,8 @@ module busfsm #(parameter integer WordCountThreshold, (BusCurrState == STATE_BUS_UNCACHED_READ); assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine); + assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; + assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; From a4c7d1d936795b435e587bcd4d42a2d94d4267f9 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 9 Jun 2022 17:50:47 -0700 Subject: [PATCH 21/28] ? --- pipelined/src/ebu/ahblite.sv | 9 +++++---- pipelined/src/lsu/busdp.sv | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 68561cbac..4b12e1a10 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -133,8 +133,9 @@ module ahblite ( assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; assign #1 HADDR = AccessAddress; - assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway - assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; + // assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway + // assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; // Commented out due to not using ISize. + assign HSIZE = (`XLEN == 64) ? 3'b011 : 3'b010; assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. @@ -167,8 +168,8 @@ module ahblite ( assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; - assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD) & HREADY; - assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState == IDLE) & (NextBusState == MEMWRITE)) & HREADY; + assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD); + assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE)); assign IFUBusAck = HREADY & (BusState == INSTRREAD); assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE)); diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index f1156b446..5139efdc1 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -68,7 +68,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic BusStall, output logic BusCommittedM); - localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 1; + localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalLSUBusAdr; logic [LOGWPL-1:0] WordCountDelayed; From 5ac17eca1d95d01d5f3e989484ea6009afabfac0 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 9 Jun 2022 18:21:13 -0700 Subject: [PATCH 22/28] Passed Regression: Seems to work perfectly fine --- pipelined/src/ebu/ahblite.sv | 5 ++--- pipelined/src/lsu/busfsm.sv | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 4b12e1a10..b25d25a4d 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -133,9 +133,8 @@ module ahblite ( assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; assign #1 HADDR = AccessAddress; - // assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway - // assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; // Commented out due to not using ISize. - assign HSIZE = (`XLEN == 64) ? 3'b011 : 3'b010; + assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway + assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 2285591cb..27156d9da 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -145,7 +145,7 @@ module busfsm #(parameter integer WordCountThreshold, assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck; - assign LSUTransType = (|WordCount) & ~UnCachedRW ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag) ? 2'b10 : 2'b00; + assign LSUTransType = (|WordCount) & ~UnCachedRW ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag | ~CACHE_ENABLED) ? 2'b10 : 2'b00; assign CntReset = BusCurrState == STATE_BUS_READY; assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | From 0e10435fb62cd6c70d7e306b786a4eff31ca1349 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 10 Jun 2022 19:10:01 -0700 Subject: [PATCH 23/28] Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01. --- pipelined/src/lsu/busfsm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 27156d9da..6e021a83b 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -147,7 +147,7 @@ module busfsm #(parameter integer WordCountThreshold, assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck; assign LSUTransType = (|WordCount) & ~UnCachedRW ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag | ~CACHE_ENABLED) ? 2'b10 : 2'b00; - assign CntReset = BusCurrState == STATE_BUS_READY; + assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine) | (WordCountFlag & LSUBusAck); assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | From 31852fdb195fcde292befb2ca5269e603be65d73 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 10 Jun 2022 20:00:09 -0700 Subject: [PATCH 24/28] Fixed failed regression state by only enabling counting when doing cached operations --- pipelined/src/lsu/busfsm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 6e021a83b..e549ee526 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -99,7 +99,7 @@ module busfsm #(parameter integer WordCountThreshold, assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); - assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag; + assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag & ~UnCachedRW; assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; From d6a1ee114178f6696741e035fbd1fa91d361e8b6 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 10 Jun 2022 20:30:04 -0700 Subject: [PATCH 25/28] Added comments to signals added so the bus is easier to analyze --- pipelined/src/lsu/busfsm.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index e549ee526..c156f6b9f 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -164,7 +164,9 @@ module busfsm #(parameter integer WordCountThreshold, (BusCurrState == STATE_BUS_UNCACHED_READ); assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine); - assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; + + // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because CacheableM is 0 when flushing cache. + assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck); From a79737e95bfdc8d5df035b5a7cb03acffcef48ec Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 10 Jun 2022 20:43:56 -0700 Subject: [PATCH 26/28] Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals --- pipelined/src/ebu/ahblite.sv | 2 +- pipelined/src/lsu/busfsm.sv | 15 +++++++++------ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index b25d25a4d..41305090d 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -119,7 +119,7 @@ module ahblite ( else if (LSUTransComplete) NextBusState = IDLE; else NextBusState = MEMREAD; MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; - else if (LSUTransComplete) NextBusState = IDLE;// Ram cannot handle a read after a write, Do not send one. + else if (LSUTransComplete) NextBusState = IDLE; else NextBusState = MEMWRITE; INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD; else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE; diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index c156f6b9f..d34221743 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -80,7 +80,7 @@ module busfsm #(parameter integer WordCountThreshold, (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; - + // Used to send address for address stage of AHB. flopenr #(LOGWPL) WordCountReg(.clk(clk), .reset(reset | CntReset), @@ -88,6 +88,7 @@ module busfsm #(parameter integer WordCountThreshold, .d(NextWordCount), .q(WordCount)); + // Used to store data from data phase of AHB. flopenr #(LOGWPL) WordCountDelayedReg(.clk(clk), .reset(reset | CntReset), @@ -98,8 +99,8 @@ module busfsm #(parameter integer WordCountThreshold, assign NextWordCount = WordCount + 1'b1; assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); - assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); - assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag & ~UnCachedRW; + assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); // Detect when we are waiting on the final access. + assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up. assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; @@ -145,9 +146,11 @@ module busfsm #(parameter integer WordCountThreshold, assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck; - assign LSUTransType = (|WordCount) & ~UnCachedRW ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag | ~CACHE_ENABLED) ? 2'b10 : 2'b00; - - assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine) | (WordCountFlag & LSUBusAck); + // Use SEQ if not doing first word, NONSEQ if doing the first read/write, and IDLE if finishing up. + assign LSUTransType = (|WordCount) & ~UnCachedRW ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~LSUTransComplete) ? 2'b10 : 2'b00; + // Reset if we aren't initiating a transaction or if we are finishing a transaction. + assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine) | LSUTransComplete; + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | From 9f4ca06f7f99f95c89ac48d8e64be5f355e344ab Mon Sep 17 00:00:00 2001 From: slmnemo Date: Mon, 13 Jun 2022 10:56:02 -0700 Subject: [PATCH 27/28] Added comment about name of LSUBusInit/Lock signal --- pipelined/src/lsu/busfsm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index d34221743..7207d0e8c 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -41,7 +41,7 @@ module busfsm #(parameter integer WordCountThreshold, input logic DCacheFetchLine, input logic DCacheWriteLine, input logic LSUBusAck, - input logic LSUBusInit, + input logic LSUBusInit, // This might be better as LSUBusLock, or to send this using LSUBusAck. input logic CPUBusy, input logic CacheableM, From a21d731834951fab4b2c4344453d7a255892a38f Mon Sep 17 00:00:00 2001 From: slmnemo Date: Mon, 13 Jun 2022 12:26:08 -0700 Subject: [PATCH 28/28] Added more comments --- pipelined/src/lsu/busfsm.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 7207d0e8c..225f2de6d 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -136,7 +136,7 @@ module busfsm #(parameter integer WordCountThreshold, always_comb begin case(WordCountThreshold) - 1: LocalBurstType = 3'b000; + 0: LocalBurstType = 3'b000; 3: LocalBurstType = 3'b011; // INCR4 7: LocalBurstType = 3'b101; // INCR8 15: LocalBurstType = 3'b111; // INCR16 @@ -144,6 +144,7 @@ module busfsm #(parameter integer WordCountThreshold, endcase end + // Would these be better as always_comb statements or muxes? assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck; // Use SEQ if not doing first word, NONSEQ if doing the first read/write, and IDLE if finishing up.