Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

Makefile

@@ -0,0 +1,26 @@
+make all: submodules other
+submodules: addins/riscv-isa-sim addins/riscv-arch-test
+	cd addins;git init; git submodule add https://github.com/riscv-non-isa/riscv-arch-test; git submodule add https://github.com/riscv-software-src/riscv-isa-sim
+	git submodule update --init --recursive
+
+other:
+	cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F
+	cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/D
+	sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include
+	sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/D/Makefile.include
+ifneq ("$(wildcard $(addins/riscv-isa-sim/build/.*))",)
+else
+	mkdir addins/riscv-isa-sim/build
+endif
+	cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin
+	make -C addins/riscv-isa-sim/
+	sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include
+	echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include
+	make -C tests/wally-riscv-arch-test
+	make -C tests/wally-riscv-arch-test XLEN=32
+	cd tests/wally-riscv-arch-test; exe2memfile.pl work/*/*/*.elf
+	make -C wally-pipelined/regression
+	
+
+
+

wally-pipelined/regression/Makefile

@@ -1,6 +1,6 @@
 make all:
-	make ../../tests/imperas-riscv-tests/
+	make -C ../../tests/imperas-riscv-tests/
-	make ../../tests/wally-riscv-arch-test/
+	make -C ../../tests/wally-riscv-arch-test/
-	make XLEN=32 ../../tests/wally-riscv-arch-test/
+	make -C XLEN=32 ../../tests/wally-riscv-arch-test/
 	exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf
 	cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh

wally-pipelined/regression/wave-all.do

@@ -492,7 +492,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdD
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD1E
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD2E
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ExtImmE
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/PreSrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ForwardedSrcAE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcBE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE

wally-pipelined/src/ieu/datapath.sv

@@ -43,6 +43,7 @@ module datapath (
   input  logic [`XLEN-1:0] PCLinkE,
   output logic [2:0]       FlagsE,
   output logic [`XLEN-1:0] PCTargetE,
+  output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
   output logic [`XLEN-1:0] SrcAE, SrcBE,
   // Memory stage signals
   input  logic             StallM, FlushM,
@@ -73,7 +74,8 @@ module datapath (
   logic [`XLEN-1:0] RD1E, RD2E;
   logic [`XLEN-1:0] ExtImmE;
 
-  logic [`XLEN-1:0] PreSrcAE, PreSrcBE, SrcAE2, SrcBE2;
+  // logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE2, SrcBE2; // *** MAde forwardedsrcae an output to get rid of a mux in the critical path.
+  logic [`XLEN-1:0] SrcAE2, SrcBE2;
 
   logic [`XLEN-1:0] ALUResultE;
   logic [`XLEN-1:0] WriteDataE;
@@ -104,12 +106,12 @@ module datapath (
   flopenrc #(5)    Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
   flopenrc #(5)    RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
 	
-  mux3  #(`XLEN)  faemux(RD1E, WriteDataW, ResultM, ForwardAE, PreSrcAE);
+  mux3  #(`XLEN)  faemux(RD1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE);
-  mux3  #(`XLEN)  fbemux(RD2E, WriteDataW, ResultM, ForwardBE, PreSrcBE);
+  mux3  #(`XLEN)  fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
-  mux2  #(`XLEN)  writedatamux(PreSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
+  mux2  #(`XLEN)  writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
-  mux2  #(`XLEN)  srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE);
+  mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
   mux2  #(`XLEN)  srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2);  
-  mux2  #(`XLEN)  srcbmux(PreSrcBE, ExtImmE, ALUSrcBE, SrcBE);
+  mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
   mux2  #(`XLEN)  srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux.
   alu   #(`XLEN)  alu(SrcAE2, SrcBE2, ALUControlE, ALUResultE, FlagsE);
   mux2  #(`XLEN)  targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE);

wally-pipelined/src/ieu/ieu.sv

@@ -40,6 +40,7 @@ module ieu (
   output logic [`XLEN-1:0] PCTargetE,
   output logic 		   MulDivE, W64E,
   output logic [2:0] 	   Funct3E,
+  output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
   output logic [`XLEN-1:0] SrcAE, SrcBE,
   input logic 		   FWriteIntM,
 

wally-pipelined/src/muldiv/intdivrestoring.sv

@@ -33,7 +33,8 @@ module intdivrestoring (
   input  logic StallM,
   input  logic DivSignedE, W64E,
   input  logic DivE,
-  input  logic [`XLEN-1:0] SrcAE, SrcBE,
+  //input logic [`XLEN-1:0] 	SrcAE, SrcBE,
+	input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
   output logic DivBusyE, 
   output logic [`XLEN-1:0] QuotM, RemM
  );
@@ -61,11 +62,11 @@ module intdivrestoring (
   // Handle sign extension for W-type instructions
   generate
     if (`XLEN == 64) begin // RV64 has W-type instructions
-      mux2 #(`XLEN) xinmux(SrcAE, {SrcAE[31:0], 32'b0}, W64E, XinE);
+      mux2 #(`XLEN) xinmux(ForwardedSrcAE, {ForwardedSrcAE[31:0], 32'b0}, W64E, XinE);
-      mux2 #(`XLEN) dinmux(SrcBE, {{32{SrcBE[31]&DivSignedE}}, SrcBE[31:0]}, W64E, DinE);
+      mux2 #(`XLEN) dinmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31]&DivSignedE}}, ForwardedSrcBE[31:0]}, W64E, DinE);
 	  end else begin // RV32 has no W-type instructions
-      assign XinE = SrcAE;
+      assign XinE = ForwardedSrcAE;
-      assign DinE = SrcBE;	    
+      assign DinE = ForwardedSrcBE;	    
     end   
   endgenerate 
 
@@ -79,7 +80,7 @@ module intdivrestoring (
   neg #(`XLEN) negd(DinE, DnE);
   mux2 #(`XLEN) dabsmux(DnE, DinE, SignDE, DAbsBE);  // take absolute value for signed operations, and negate for subtraction setp
   neg #(`XLEN) negx(XinE, XnE);
-  mux3 #(`XLEN) xabsmux(XinE, XnE, SrcAE, {Div0E, SignXE}, XInitE);  // take absolute value for signed operations, or keep original value for divide by 0
+  mux3 #(`XLEN) xabsmux(XinE, XnE, ForwardedSrcAE, {Div0E, SignXE}, XInitE);  // take absolute value for signed operations, or keep original value for divide by 0
 
   // initialization multiplexers on first cycle of operation
   mux2 #(`XLEN) wmux(WM[`DIV_BITSPERCYCLE], {`XLEN{1'b0}}, DivStartE, WNextE);

wally-pipelined/src/muldiv/mul.sv

@@ -29,7 +29,8 @@ module mul (
   // Execute Stage interface
   input  logic             clk, reset,
   input  logic             StallM, FlushM,
-  input  logic [`XLEN-1:0] SrcAE, SrcBE,
+    //    input logic [`XLEN-1:0] 	SrcAE, SrcBE,
+  input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
   input  logic [2:0]       Funct3E,
   output logic [`XLEN*2-1:0] ProdM
 );
@@ -59,12 +60,12 @@ module mul (
   // Execute Stage: Compute partial products
   //////////////////////////////
 
-    assign Aprime = {1'b0, SrcAE[`XLEN-2:0]};
+    assign Aprime = {1'b0, ForwardedSrcAE[`XLEN-2:0]};
-    assign Bprime = {1'b0, SrcBE[`XLEN-2:0]};
+    assign Bprime = {1'b0, ForwardedSrcBE[`XLEN-2:0]};
     redundantmul #(`XLEN) bigmul(.a(Aprime), .b(Bprime), .out0(PP0E), .out1(PP1E));
-    assign PA = {(`XLEN-1){SrcAE[`XLEN-1]}} & SrcBE[`XLEN-2:0];  
+    assign PA = {(`XLEN-1){ForwardedSrcAE[`XLEN-1]}} & ForwardedSrcBE[`XLEN-2:0];  
-    assign PB = {(`XLEN-1){SrcBE[`XLEN-1]}} & SrcAE[`XLEN-2:0];
+    assign PB = {(`XLEN-1){ForwardedSrcBE[`XLEN-1]}} & ForwardedSrcAE[`XLEN-2:0];
-    assign PP = SrcAE[`XLEN-1] & SrcBE[`XLEN-1];
+    assign PP = ForwardedSrcAE[`XLEN-1] & ForwardedSrcBE[`XLEN-1];
 
     // flavor of multiplication
     assign MULH   = (Funct3E == 3'b001);
@@ -88,6 +89,6 @@ module mul (
 	 flopenrc #(`XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M); 
 	 flopenrc #(`XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M); 
 
-    assign ProdM = PP0M + PP1M + PP2M + PP3M + PP4M; //SrcAE * SrcBE;
+    assign ProdM = PP0M + PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE;
  endmodule
 

wally-pipelined/src/muldiv/muldiv.sv

@@ -28,7 +28,8 @@
 module muldiv (
 	       input logic 		clk, reset,
 	       // Execute Stage interface
-	       input logic [`XLEN-1:0] 	SrcAE, SrcBE,
+	       //    input logic [`XLEN-1:0] 	SrcAE, SrcBE,
+		   input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
 	       input logic [2:0] 	Funct3E, Funct3M,
 	       input logic 		MulDivE, W64E,
 	       // Writeback stage
@@ -62,7 +63,7 @@ module muldiv (
 	 assign DivE = MulDivE & Funct3E[2];
 	 assign DivSignedE = ~Funct3E[0];
 	 intdivrestoring div(.clk, .reset, .StallM,
-	   .DivSignedE, .W64E, .DivE, .SrcAE, .SrcBE, .DivBusyE, .QuotM, .RemM);
+	   .DivSignedE, .W64E, .DivE, .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
 	 	 
 	 // Result multiplexer
 	 always_comb

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -59,7 +59,7 @@ module wallypipelinedhart (
   logic 		    CSRReadM, CSRWriteM, PrivilegedM;
   logic [1:0] 		    AtomicE;
   logic [1:0] 		    AtomicM;
-  logic [`XLEN-1:0] 	    SrcAE, SrcBE;
+  logic [`XLEN-1:0] 	ForwardedSrcAE, ForwardedSrcBE, SrcAE, SrcBE;
   logic [`XLEN-1:0] 	    SrcAM;
   logic [2:0] 		    Funct3E;
   //  logic [31:0] InstrF;
@@ -158,24 +158,39 @@ module wallypipelinedhart (
     .clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW,
     .FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
-    .InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF, 
+
+    // Fetch
+    .InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF,
+    .InstrReadF, .ICacheStallF,
+
+    // Execute
     .PCLinkE, .PCSrcE, .PCTargetE, .PCE,
     .BPPredWrongE, 
-    .RetM, .TrapM, 
+  
-    .PrivilegedNextPCM, .InvalidateICacheM,
+    // Mem
-    .InstrD, .InstrM, 
+    .RetM, .TrapM, .PrivilegedNextPCM, .InvalidateICacheM,
-    .PCM, .InstrClassM, 
+    .InstrD, .InstrM, . PCM, .InstrClassM, .BPPredDirWrongM,
-    .BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
+    .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
-    .IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD,
+  
-    .InstrMisalignedFaultM, .InstrMisalignedAdrM,
+    // Writeback
+
+    // output logic
+    // Faults
+    .IllegalBaseInstrFaultD, .ITLBInstrPageFaultF,
+    .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
+    .InstrMisalignedAdrM,
+
+    // mmu management
     .PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
-    .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+    .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
-    .ITLBWriteF, .ITLBFlushF,
+    .STATUS_MPP, .ITLBWriteF, .ITLBFlushF,
-    .WalkerInstrPageFaultF,
+    .WalkerInstrPageFaultF, .ITLBMissF,
-    .ITLBMissF,
+
-    .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
+    // pmp/pma (inside mmu) signals.  *** temporarily from AHB bus but eventually replace with internal versions pre H
+    .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW,
     .InstrAccessFaultF
 
+	  
 	  ); // instruction fetch unit: PC, branch prediction, instruction cache