added some explanatory comments

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S

@@ -36,7 +36,7 @@ WRITE_READ_CSR mie, 0xFFF
 // test 5.3.1.6 Interrupt enabling and priority tests 
 
 // Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling 
-jal cause_m_soft_interrupt
+jal cause_m_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
 
 li x28, 0x8
 csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S

@@ -40,7 +40,7 @@ WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
 GOTO_S_MODE
 
 // Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling 
-jal cause_s_soft_interrupt
+jal cause_s_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
 
 li x28, 0x2
 csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S

@@ -37,7 +37,7 @@ WRITE_READ_CSR mie, 0xFFF
 
 // cause traps, ensuring that we DONT go through the vectored part of the trap handler
 
-jal cause_m_time_interrupt
+jal cause_m_time_interrupt // *** only cause one interrupt because we just want to test the status stack
 
 END_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S

@@ -41,7 +41,7 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
 
 GOTO_S_MODE
 
-jal cause_s_soft_interrupt
+jal cause_s_soft_interrupt // *** only cause one interrupt since we just want to test the tvec csr
 
 GOTO_M_MODE