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Another change required for forcing to work correctly with MIE/MIP and SIE/SIP.

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This commit is contained in:
Ross Thompson 2022-03-23 10:26:17 -05:00
parent f1787670d4
commit c55c5eec82
1 changed files with 14 additions and 12 deletions
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26
pipelined/src/privileged/csri.sv
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@ -95,20 +95,22 @@ module csri #(parameter
// else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field // else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field
// restricted views of registers // restricted views of registers
// Add MEIP read-only signal assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
always_comb begin:regs
// Add MEIP read-only signal
// Machine Mode // Machine Mode
assign MIP_REGW = IP_REGW; MIP_REGW = IP_REGW;
assign MIE_REGW = IE_REGW; MIE_REGW = IE_REGW;
// Supervisor mode // Supervisor mode
if (`S_SUPPORTED) begin if (`S_SUPPORTED) begin
assign SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible
assign SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222; SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222;
end else begin end else begin
assign SIP_REGW = 12'b0; SIP_REGW = 12'b0;
assign SIE_REGW = 12'b0; SIE_REGW = 12'b0;
end
end end
endmodule endmodule