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Ross Thompson 2023-01-20 11:51:10 -06:00
parent 5b5a615e4a
commit c5169a3e39
4 changed files with 76 additions and 66 deletions
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11
pipelined/src/generic/mem/ram1p1rwbe.sv
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@ -1,14 +1,17 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// 1 port sram. // 1 port sram.
// //
// Written: ross1728@gmail.com May 3, 2021 // Written: ross1728@gmail.com
// Created: 3 May 2021
// Modified: 20 January 2023
//
// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
// Basic sram with 1 read write port. // Basic sram with 1 read write port.
// When clk rises Addr and LineWriteData are sampled. // When clk rises Addr and LineWriteData are sampled.
// Following the clk edge read data is output from the sampled Addr. // Following the clk edge read data is output from the sampled Addr.
// Write
//
// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
// //
// Documentation:
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

20
pipelined/src/ifu/bpred.sv
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@ -38,13 +38,13 @@ module bpred (
input logic [`XLEN-1:0] PCNextF, // Next Fetch Address input logic [`XLEN-1:0] PCNextF, // Next Fetch Address
input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4
output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction
output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage. output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage
// Update Predictor // Update Predictor
input logic [`XLEN-1:0] PCF, // Fetch stage instruction address. input logic [`XLEN-1:0] PCF, // Fetch stage instruction address
input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took. input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took
input logic [`XLEN-1:0] PCE, // Execution stage instruction address. input logic [`XLEN-1:0] PCE, // Execution stage instruction address
input logic [`XLEN-1:0] PCM, // Memory stage instruction address. input logic [`XLEN-1:0] PCM, // Memory stage instruction address
// Branch and jump outcome // Branch and jump outcome
input logic PCSrcE, // Executation stage branch is taken input logic PCSrcE, // Executation stage branch is taken
@ -53,11 +53,11 @@ module bpred (
output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
// Report branch prediction status // Report branch prediction status
output logic BPPredWrongE, // Prediction is wrong. output logic BPPredWrongE, // Prediction is wrong
output logic DirPredictionWrongM, // Prediction direction is wrong. output logic DirPredictionWrongM, // Prediction direction is wrong
output logic BTBPredPCWrongM, // Prediction target wrong. output logic BTBPredPCWrongM, // Prediction target wrong
output logic RASPredPCWrongM, // RAS prediction is wrong. output logic RASPredPCWrongM, // RAS prediction is wrong
output logic PredictionInstrClassWrongM // Class prediction is wrong. output logic PredictionInstrClassWrongM // Class prediction is wrong
); );
logic BTBValidF; logic BTBValidF;

105
pipelined/src/ifu/ifu.sv
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@ -28,58 +28,65 @@
`include "wally-config.vh" `include "wally-config.vh"
module ifu ( module ifu (
input logic clk, reset, input logic clk, reset,
input logic StallF, StallD, StallE, StallM, StallW, input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
(* mark_debug = "true" *) output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation
// Command from CPU
input logic InvalidateICacheM, // Clears all instruction cache valid bits
input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
// Bus interface // Bus interface
(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU
(* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) input logic IFUHREADY, // Bus ready from IFU to EBU
(* mark_debug = "true" *) output logic [2:0] IFUHBURST, (* mark_debug = "true" *) output logic IFUHWRITE, // Bus write operation from IFU to EBU
(* mark_debug = "true" *) output logic [1:0] IFUHTRANS, (* mark_debug = "true" *) output logic [2:0] IFUHSIZE, // Bus operation size from IFU to EBU
(* mark_debug = "true" *) output logic [2:0] IFUHSIZE, (* mark_debug = "true" *) output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU
(* mark_debug = "true" *) output logic IFUHWRITE, (* mark_debug = "true" *) output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU
(* mark_debug = "true" *) input logic IFUHREADY,
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Fetch stage instruction address
// Execute // Execute
output logic [`XLEN-1:0] PCLinkE, output logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
input logic PCSrcE, input logic PCSrcE, // Executation stage branch is taken
input logic [`XLEN-1:0] IEUAdrE, input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
output logic [`XLEN-1:0] PCE, output logic [`XLEN-1:0] PCE, // Execution stage instruction address
output logic BPPredWrongE, output logic BPPredWrongE, // Prediction is wrong
// Mem // Mem
output logic CommittedF, output logic CommittedF, // I$ or bus memory operation started, delay interrupts
input logic [`XLEN-1:0] UnalignedPCNextF, input logic [`XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes.
output logic [`XLEN-1:0] PCNext2F, output logic [`XLEN-1:0] PCNext2F, // Selected PC between branch prediction and next valid PC if CSRWriteFence
input logic CSRWriteFenceM, output logic [31:0] InstrD, // The decoded instruction in Decode stage
input logic InvalidateICacheM, output logic [31:0] InstrM, // The decoded instruction in Memory stage
output logic [31:0] InstrD, InstrM, output logic [`XLEN-1:0] PCM, // Memory stage instruction address
output logic [`XLEN-1:0] PCM, // branch predictor
// branch predictor output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
output logic [3:0] InstrClassM, output logic DirPredictionWrongM, // Prediction direction is wrong
output logic DirPredictionWrongM, output logic BTBPredPCWrongM, // Prediction target wrong
output logic BTBPredPCWrongM, output logic RASPredPCWrongM, // RAS prediction is wrong
output logic RASPredPCWrongM, output logic PredictionInstrClassWrongM, // Class prediction is wrong
output logic PredictionInstrClassWrongM, // Faults
// Faults input logic IllegalBaseInstrFaultD, // Illegal non-compressed instruction
input logic IllegalBaseInstrFaultD, output logic InstrPageFaultF, // Instruction page fault
output logic InstrPageFaultF, output logic IllegalIEUInstrFaultD, // Illegal instruction including compressed
output logic IllegalIEUInstrFaultD, output logic InstrMisalignedFaultM, // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
output logic InstrMisalignedFaultM, // mmu management
// mmu management input logic [1:0] PrivilegeModeW, // Priviledge mode in Writeback stage
input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] PTE, // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
input logic [`XLEN-1:0] PTE, input logic [1:0] PageType, // Hardware page table walker (HPTW) writes PageType to ITLB
input logic [1:0] PageType, input logic ITLBWriteF, // Writes PTE and PageType to ITLB
input logic [`XLEN-1:0] SATP_REGW, input logic [`XLEN-1:0] SATP_REGW, // Location of the root page table and page table configuration
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, // Status CSR: make executable page readable
input logic [1:0] STATUS_MPP, input logic STATUS_SUM, // Status CSR: Supervisor access to user memory
input logic ITLBWriteF, sfencevmaM, input logic STATUS_MPRV, // Status CSR: modify machine privilege
output logic ITLBMissF, InstrDAPageFaultF, input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
output logic InstrAccessFaultF, output logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits
output logic ICacheAccess, input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
output logic ICacheMiss input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
output logic InstrAccessFaultF,
output logic ICacheAccess,
output logic ICacheMiss
); );
(* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF; (* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF;
logic BranchMisalignedFaultE; logic BranchMisalignedFaultE;

6
pipelined/src/lsu/lsu.sv
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@ -34,7 +34,7 @@
module lsu ( module lsu (
input logic clk, reset, input logic clk, reset,
input logic StallM, FlushM, StallW, FlushW, input logic StallM, FlushM, StallW, FlushW,
output logic LSUStallM, // LSU stalls pipeline during a multicycle operation. output logic LSUStallM, // LSU stalls pipeline during a multicycle operation
// connected to cpu (controls) // connected to cpu (controls)
input logic [1:0] MemRWM, // Read/Write control input logic [1:0] MemRWM, // Read/Write control
input logic [2:0] Funct3M, // Size of memory operation input logic [2:0] Funct3M, // Size of memory operation
@ -53,7 +53,7 @@ module lsu (
// cpu privilege // cpu privilege
input logic [1:0] PrivilegeModeW, // Current privilege mode input logic [1:0] PrivilegeModeW, // Current privilege mode
input logic BigEndianM, // Swap byte order to big endian input logic BigEndianM, // Swap byte order to big endian
input logic sfencevmaM, // Virtual memory address fence input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
// fpu // fpu
input logic [`FLEN-1:0] FWriteDataM, // Write data from FPU input logic [`FLEN-1:0] FWriteDataM, // Write data from FPU
input logic FpLoadStoreM, // Selects FPU as store for write data input logic FpLoadStoreM, // Selects FPU as store for write data
@ -126,7 +126,7 @@ module lsu (
logic [(`LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write logic [(`LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write
logic DTLBMissM; // DTLB miss causes HPTW walk logic DTLBMissM; // DTLB miss causes HPTW walk
logic DTLBWriteM; // Writes PTE to DTLB logic DTLBWriteM; // Writes PTE and PageType to DTLB
logic DataDAPageFaultM; // DTLB hit needs to update dirty or access bits logic DataDAPageFaultM; // DTLB hit needs to update dirty or access bits
logic LSULoadAccessFaultM; // Load acces fault logic LSULoadAccessFaultM; // Load acces fault
logic LSUStoreAmoAccessFaultM; // Store access fault logic LSUStoreAmoAccessFaultM; // Store access fault