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https://github.com/openhwgroup/cvw
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Changes made on 9th Jun
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8ae57f075f
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@ -115,11 +115,11 @@ module ahblite (
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else if (LSUBusWrite) NextBusState = MEMWRITE;
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else if (LSUBusWrite) NextBusState = MEMWRITE;
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else if (IFUBusRead) NextBusState = INSTRREAD;
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else if (IFUBusRead) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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else NextBusState = IDLE;
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MEMREAD: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD;
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MEMREAD: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD;
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else if (LSUTransComplete) NextBusState = IDLE;
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else if (LSUTransComplete) NextBusState = IDLE;
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else NextBusState = MEMREAD;
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else NextBusState = MEMREAD;
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MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD;
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MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD;
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else if (LSUTransComplete) NextBusState = IDLE;
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else if (LSUTransComplete) NextBusState = IDLE;// Ram cannot handle a read after a write, Do not send one.
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else NextBusState = MEMWRITE;
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else NextBusState = MEMWRITE;
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INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD;
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INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD;
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else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE;
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else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE;
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@ -155,7 +155,7 @@ module ahblite (
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assign HMASTLOCK = 0; // no locking supported
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assign HMASTLOCK = 0; // no locking supported
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assign HWRITE = (NextBusState == MEMWRITE);
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assign HWRITE = (NextBusState == MEMWRITE);
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// delay write data by one cycle for
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// delay write data by one cycle for
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flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck | IFUBusInit | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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// delay signals for subword writes
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// delay signals for subword writes
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flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
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flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
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flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
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flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
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@ -167,8 +167,8 @@ module ahblite (
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assign IFUBusHRDATA = HRDATA;
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assign IFUBusHRDATA = HRDATA;
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assign LSUBusHRDATA = HRDATA;
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assign LSUBusHRDATA = HRDATA;
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assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD);
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assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD) & HREADY;
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assign LSUBusInit = ((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState == IDLE) & (NextBusState == MEMWRITE);
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assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState == IDLE) & (NextBusState == MEMWRITE)) & HREADY;
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assign IFUBusAck = HREADY & (BusState == INSTRREAD);
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assign IFUBusAck = HREADY & (BusState == INSTRREAD);
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assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE));
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assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE));
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@ -68,7 +68,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
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output logic BusStall,
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output logic BusStall,
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output logic BusCommittedM);
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output logic BusCommittedM);
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localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
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localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 1;
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logic [`PA_BITS-1:0] LocalLSUBusAdr;
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logic [`PA_BITS-1:0] LocalLSUBusAdr;
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logic [LOGWPL-1:0] WordCountDelayed;
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logic [LOGWPL-1:0] WordCountDelayed;
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@ -65,7 +65,7 @@ module busfsm #(parameter integer WordCountThreshold,
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logic CntReset;
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logic CntReset;
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logic WordCountFlag;
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logic WordCountFlag;
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logic [LOGWPL-1:0] NextWordCount;
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logic [LOGWPL-1:0] NextWordCount;
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logic UnCachedAccess;
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logic UnCachedAccess, UnCachedRW;
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logic [2:0] LocalBurstType;
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logic [2:0] LocalBurstType;
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@ -97,6 +97,7 @@ module busfsm #(parameter integer WordCountThreshold,
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assign NextWordCount = WordCount + 1'b1;
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assign NextWordCount = WordCount + 1'b1;
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assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE);
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assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]);
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assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]);
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assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag;
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assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag;
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@ -138,21 +139,20 @@ module busfsm #(parameter integer WordCountThreshold,
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3: LocalBurstType = 3'b011; // INCR4
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3: LocalBurstType = 3'b011; // INCR4
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7: LocalBurstType = 3'b101; // INCR8
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7: LocalBurstType = 3'b101; // INCR8
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15: LocalBurstType = 3'b111; // INCR16
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15: LocalBurstType = 3'b111; // INCR16
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default: LocalBurstType = 3'b001; // No Burst
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default: LocalBurstType = 3'b001; // INCR without end.
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endcase
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endcase
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end
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end
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assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access.
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assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access.
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assign LSUTransComplete = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck;
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assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck;
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assign LSUTransType = (|WordCount) & ~UnCachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag | UnCachedAccess) ? 2'b10 : 2'b00;
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assign LSUTransType = (|WordCount) & ~UnCachedRW ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag) ? 2'b10 : 2'b00;
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assign CntReset = (BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine)) | LSUTransComplete;
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assign CntReset = BusCurrState == STATE_BUS_READY;
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assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) |
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assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) |
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(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
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(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
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(BusCurrState == STATE_BUS_UNCACHED_READ) |
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(BusCurrState == STATE_BUS_UNCACHED_READ) |
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(BusCurrState == STATE_BUS_FETCH) |
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(BusCurrState == STATE_BUS_FETCH) |
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(BusCurrState == STATE_BUS_WRITE);
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(BusCurrState == STATE_BUS_WRITE);
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assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE;
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assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) |
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assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) |
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(BusCurrState == STATE_BUS_UNCACHED_WRITE);
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(BusCurrState == STATE_BUS_UNCACHED_WRITE);
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assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE);
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assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE);
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@ -164,6 +164,8 @@ module busfsm #(parameter integer WordCountThreshold,
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(BusCurrState == STATE_BUS_UNCACHED_READ);
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(BusCurrState == STATE_BUS_UNCACHED_READ);
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assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);
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assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);
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assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead;
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assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) |
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assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) |
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(BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck);
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(BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck);
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assign BusCommittedM = BusCurrState != STATE_BUS_READY;
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assign BusCommittedM = BusCurrState != STATE_BUS_READY;
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