From b8522c49870def657dc013433000c0e5d803eb7b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 24 Aug 2023 09:00:17 -0700 Subject: [PATCH 1/4] update wrappers --- src/wrappers/drsuwrapper.sv | 7 ++++--- src/wrappers/fdivsqrt.sv | 0 src/wrappers/wallypipelinedcorewrapper.sv | 10 +++++----- 3 files changed, 9 insertions(+), 8 deletions(-) delete mode 100644 src/wrappers/fdivsqrt.sv diff --git a/src/wrappers/drsuwrapper.sv b/src/wrappers/drsuwrapper.sv index cb97a4aab..dae37e5bb 100644 --- a/src/wrappers/drsuwrapper.sv +++ b/src/wrappers/drsuwrapper.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// drsu.sv +// drsuwrapper.sv // // Written: kekim@hmc.edu // Modified:19 May 2023 @@ -29,7 +29,8 @@ import cvw::*; -module drsuwrapper( +`include "parameter-defs.vh" +module drsuwrapper ( input logic clk, input logic reset, input logic [1:0] FmtE, @@ -57,7 +58,7 @@ module drsuwrapper( ); //`include "parameter-defs.vh" -drsu #(P) d(.*); + drsu #(P) drsucore(.*); endmodule \ No newline at end of file diff --git a/src/wrappers/fdivsqrt.sv b/src/wrappers/fdivsqrt.sv deleted file mode 100644 index e69de29bb..000000000 diff --git a/src/wrappers/wallypipelinedcorewrapper.sv b/src/wrappers/wallypipelinedcorewrapper.sv index bc5f63d1c..1d8f4f774 100644 --- a/src/wrappers/wallypipelinedcorewrapper.sv +++ b/src/wrappers/wallypipelinedcorewrapper.sv @@ -30,18 +30,19 @@ import cvw::*; +`include "parameter-defs.vh" module wallypipelinedcorewrapper ( input logic clk, reset, // Privileged input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, // Bus Interface - input logic [AHBW-1:0] HRDATA, + input logic [32-1:0] HRDATA, input logic HREADY, HRESP, output logic HCLK, HRESETn, - output logic [PA_BITS-1:0] HADDR, - output logic [AHBW-1:0] HWDATA, - output logic [XLEN/8-1:0] HWSTRB, + output logic [34-1:0] HADDR, + output logic [32-1:0] HWDATA, + output logic [32/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -49,7 +50,6 @@ module wallypipelinedcorewrapper ( output logic [1:0] HTRANS, output logic HMASTLOCK ); - `include "parameter-defs.vh" wallypipelinedcore #(P) core(.*); From 7cb3d87554556b4b7428d1324c09981d19cdb989 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 24 Aug 2023 09:19:23 -0700 Subject: [PATCH 2/4] synth fix --- synthDC/scripts/synth.tcl | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 7a8c2e7bf..8bb5140fa 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -24,8 +24,7 @@ set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) -eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} -eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} +eval file copy -force [glob ${cfg}/*.vh] {$outputDir/config/} eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} From bfba32dfd989972c06cf392c2f5972cb1281d49e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 26 Aug 2023 20:20:20 -0700 Subject: [PATCH 3/4] synthesis works --- config/shared/parameter-defs.vh | 2 +- {src/wrappers => fpga/src}/drsuwrapper.sv | 0 src/wrappers/wallypipelinedcorewrapper.sv | 4 ++-- synthDC/scripts/synth.tcl | 9 ++++----- 4 files changed, 7 insertions(+), 8 deletions(-) rename {src/wrappers => fpga/src}/drsuwrapper.sv (100%) diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 6e01aabb4..9ce59950e 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -3,7 +3,7 @@ `include "BranchPredictorType.vh" -parameter cvw_t P = '{ +localparam cvw_t P = '{ FPGA : FPGA, XLEN : XLEN, IEEE754 : IEEE754, diff --git a/src/wrappers/drsuwrapper.sv b/fpga/src/drsuwrapper.sv similarity index 100% rename from src/wrappers/drsuwrapper.sv rename to fpga/src/drsuwrapper.sv diff --git a/src/wrappers/wallypipelinedcorewrapper.sv b/src/wrappers/wallypipelinedcorewrapper.sv index 1d8f4f774..09309bf0e 100644 --- a/src/wrappers/wallypipelinedcorewrapper.sv +++ b/src/wrappers/wallypipelinedcorewrapper.sv @@ -37,10 +37,10 @@ module wallypipelinedcorewrapper ( input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, // Bus Interface - input logic [32-1:0] HRDATA, + input logic [P.XLEN-1:0] HRDATA, input logic HREADY, HRESP, output logic HCLK, HRESETn, - output logic [34-1:0] HADDR, + output logic [P.PA_BITS-1:0] HADDR, output logic [32-1:0] HWDATA, output logic [32/8-1:0] HWSTRB, output logic HWRITE, diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 8bb5140fa..a5b435c13 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -25,20 +25,19 @@ set maxopt $::env(MAXOPT) set drive $::env(DRIVE) eval file copy -force [glob ${cfg}/*.vh] {$outputDir/config/} +eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} -eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} +#eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} -# Only for FMA class project; comment out when done -# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} - # Enables name mapping if { $saifpower == 1 } { saif_map -start } # Verilog files +#set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv $outputDir/config/*.vh] set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv] # Set toplevel @@ -75,7 +74,7 @@ if { [shell_is_in_topographical_mode] } { #set alib_library_analysis_path ./$outputDir define_design_lib WORK -path ./$outputDir/WORK analyze -f sverilog -lib WORK $my_verilog_files -elaborate $my_toplevel -parameter P -lib WORK +elaborate $my_toplevel -lib WORK # Set the current_design current_design $my_toplevel From e75c5d46e4925a378096854c977f00ae5ec67055 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 26 Aug 2023 20:25:47 -0700 Subject: [PATCH 4/4] created wrappers directory in synth/ --- {fpga/src => synthDC/wrappers}/drsuwrapper.sv | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename {fpga/src => synthDC/wrappers}/drsuwrapper.sv (100%) diff --git a/fpga/src/drsuwrapper.sv b/synthDC/wrappers/drsuwrapper.sv similarity index 100% rename from fpga/src/drsuwrapper.sv rename to synthDC/wrappers/drsuwrapper.sv