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Fixed another critical path in the caches.

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This commit is contained in:
Ross Thompson 2021-10-25 22:05:11 -05:00
parent 1228dbbebc
commit c43b19120f
1 changed files with 26 additions and 7 deletions
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33
wally-pipelined/src/cache/cacheway.sv vendored
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@ -64,6 +64,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
logic [TAGLEN-1:0] VicDirtyWay; logic [TAGLEN-1:0] VicDirtyWay;
logic [TAGLEN-1:0] FlushThisWay; logic [TAGLEN-1:0] FlushThisWay;
logic [$clog2(NUMLINES)-1:0] RAdrD, WAdrD;
logic SetValidD, ClearValidD;
logic SetDirtyD, ClearDirtyD;
logic WriteEnableD, VDWriteEnableD;
genvar words; genvar words;
generate generate
@ -108,28 +116,39 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
ValidBits <= {NUMLINES{1'b0}}; ValidBits <= {NUMLINES{1'b0}};
else if (InvalidateAll) else if (InvalidateAll)
ValidBits <= {NUMLINES{1'b0}}; ValidBits <= {NUMLINES{1'b0}};
else if (SetValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b1; else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[WAdrD] <= 1'b1;
else if (ClearValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b0; else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[WAdrD] <= 1'b0;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
Valid <= ValidBits[RAdr]; RAdrD <= RAdr;
WAdrD <= WAdr;
SetValidD <= SetValid;
ClearValidD <= ClearValid;
WriteEnableD <= WriteEnable;
VDWriteEnableD <= VDWriteEnable;
end end
assign Valid = ValidBits[RAdrD];
generate generate
if(DIRTY_BITS) begin if(DIRTY_BITS) begin
always_ff @(posedge clk, posedge reset) begin always_ff @(posedge clk, posedge reset) begin
if (reset) if (reset)
DirtyBits <= {NUMLINES{1'b0}}; DirtyBits <= {NUMLINES{1'b0}};
else if (SetDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b1; else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1;
else if (ClearDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b0; else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk, posedge reset) begin
Dirty <= DirtyBits[RAdr]; SetDirtyD <= SetDirty;
ClearDirtyD <= ClearDirty;
end end
assign Dirty = DirtyBits[RAdrD];
end else begin end else begin
assign Dirty = 1'b0; assign Dirty = 1'b0;
end end