mirror of
https://github.com/openhwgroup/cvw
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XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
commit
c42967f5c6
80
pipelined/src/cache/cachefsm.sv
vendored
80
pipelined/src/cache/cachefsm.sv
vendored
@ -81,13 +81,13 @@ module cachefsm
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typedef enum logic [3:0] {STATE_READY, // hit states
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typedef enum logic [3:0] {STATE_READY, // hit states
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// miss states
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// miss states
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STATE_MISS_FETCH_WDV,
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STATE_FETCH,
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STATE_MISS_EVICT_DIRTY,
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STATE_WRITEBACK,
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STATE_MISS_WRITE_CACHE_LINE,
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STATE_WRITE_LINE,
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STATE_MISS_READ_DELAY, // required for back to back reads. structural hazard on writting SRAM
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STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM
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// flush cache
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// flush cache
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STATE_FLUSH,
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STATE_FLUSH,
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STATE_FLUSH_WRITE_BACK} statetype;
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STATE_FLUSH_WRITEBACK} statetype;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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@ -119,23 +119,23 @@ module cachefsm
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else if(FlushCache) NextState = STATE_FLUSH;
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else if(FlushCache) NextState = STATE_FLUSH;
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// Delayed LRU update. Cannot check if victim line is dirty on this cycle.
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// Delayed LRU update. Cannot check if victim line is dirty on this cycle.
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// To optimize do the fetch first, then eviction if necessary.
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// To optimize do the fetch first, then eviction if necessary.
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else if(AnyMiss & ~LineDirty) NextState = STATE_MISS_FETCH_WDV;
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else if(AnyMiss & ~LineDirty) NextState = STATE_FETCH;
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else if(AnyMiss & LineDirty) NextState = STATE_MISS_EVICT_DIRTY;
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else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK;
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else NextState = STATE_READY;
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else NextState = STATE_READY;
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STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
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STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
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else NextState = STATE_MISS_FETCH_WDV;
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else NextState = STATE_FETCH;
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STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_DELAY;
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STATE_WRITE_LINE: NextState = STATE_READ_HOLD;
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STATE_MISS_READ_DELAY: if(Stall) NextState = STATE_MISS_READ_DELAY;
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STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD;
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else NextState = STATE_READY;
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else NextState = STATE_READY;
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STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_FETCH_WDV;
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STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH;
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else NextState = STATE_MISS_EVICT_DIRTY;
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else NextState = STATE_WRITEBACK;
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// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
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// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
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STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITE_BACK;
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STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK;
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else if (FlushFlag) NextState = STATE_MISS_READ_DELAY;
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else if (FlushFlag) NextState = STATE_READ_HOLD;
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else NextState = STATE_FLUSH;
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else NextState = STATE_FLUSH;
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STATE_FLUSH_WRITE_BACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH;
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STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH;
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else if(CacheBusAck) NextState = STATE_MISS_READ_DELAY;
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else if(CacheBusAck) NextState = STATE_READ_HOLD;
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else NextState = STATE_FLUSH_WRITE_BACK;
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else NextState = STATE_FLUSH_WRITEBACK;
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default: NextState = STATE_READY;
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default: NextState = STATE_READY;
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endcase
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endcase
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end
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end
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@ -143,48 +143,48 @@ module cachefsm
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// com back to CPU
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// com back to CPU
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assign CacheCommitted = CurrState != STATE_READY;
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assign CacheCommitted = CurrState != STATE_READY;
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assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) |
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assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) |
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(CurrState == STATE_MISS_FETCH_WDV) |
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(CurrState == STATE_FETCH) |
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(CurrState == STATE_MISS_EVICT_DIRTY) |
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(CurrState == STATE_WRITEBACK) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(StoreAMO)) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
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(CurrState == STATE_WRITE_LINE & ~(StoreAMO)) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
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(CurrState == STATE_FLUSH) |
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(CurrState == STATE_FLUSH) |
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(CurrState == STATE_FLUSH_WRITE_BACK);
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(CurrState == STATE_FLUSH_WRITEBACK);
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// write enables internal to cache
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// write enables internal to cache
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assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
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assign SetValid = CurrState == STATE_WRITE_LINE;
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assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) |
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assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE & (StoreAMO));
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(CurrState == STATE_WRITE_LINE & (StoreAMO));
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assign ClearValid = '0;
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assign ClearValid = '0;
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assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(StoreAMO)) |
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assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) |
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(CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set.
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(CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set.
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assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) |
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assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE);
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(CurrState == STATE_WRITE_LINE);
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// Flush and eviction controls
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// Flush and eviction controls
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assign SelWriteback = (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
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assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
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(CurrState == STATE_READY & AnyMiss & LineDirty);
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(CurrState == STATE_READY & AnyMiss & LineDirty);
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assign SelFlush = (CurrState == STATE_READY & FlushCache) |
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assign SelFlush = (CurrState == STATE_READY & FlushCache) |
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(CurrState == STATE_FLUSH) |
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(CurrState == STATE_FLUSH) |
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(CurrState == STATE_FLUSH_WRITE_BACK);
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(CurrState == STATE_FLUSH_WRITEBACK);
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assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayFlag & CacheBusAck) |
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assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) |
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(CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
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(CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
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assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) |
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assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) |
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(CurrState == STATE_FLUSH_WRITE_BACK & CacheBusAck);
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(CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck);
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assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) |
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assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) |
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(CurrState == STATE_FLUSH_WRITE_BACK & FlushFlag & CacheBusAck);
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(CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck);
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// Bus interface controls
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// Bus interface controls
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assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) |
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assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) |
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(CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) |
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(CurrState == STATE_FETCH & ~CacheBusAck) |
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(CurrState == STATE_MISS_EVICT_DIRTY & CacheBusAck);
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(CurrState == STATE_WRITEBACK & CacheBusAck);
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assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) |
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assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) |
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(CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
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(CurrState == STATE_WRITEBACK & ~CacheBusAck) |
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(CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck);
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(CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck);
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// **** can this be simplified?
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// **** can this be simplified?
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assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // changes if store delay hazard removed
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assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // changes if store delay hazard removed
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(CurrState == STATE_MISS_FETCH_WDV) |
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(CurrState == STATE_FETCH) |
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(CurrState == STATE_MISS_EVICT_DIRTY) |
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(CurrState == STATE_WRITEBACK) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
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(CurrState == STATE_WRITE_LINE) |
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resetDelay;
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resetDelay;
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assign SelFetchBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE | CurrState == STATE_MISS_READ_DELAY;
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assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
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assign CacheEn = (CurrState == STATE_READY & ~Stall | CacheStall) | (CurrState != STATE_READY) | reset;
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assign CacheEn = (CurrState == STATE_READY & (~Stall | FlushCache | AnyMiss)) | (CurrState != STATE_READY) | reset;
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endmodule // cachefsm
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endmodule // cachefsm
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@ -66,29 +66,29 @@ module fdivsqrt(
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logic Firstun;
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logic Firstun;
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logic WZeroM, AZeroM, BZeroM, AZeroE, BZeroE;
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logic WZeroM, AZeroM, BZeroM, AZeroE, BZeroE;
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logic SpecialCaseM;
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logic SpecialCaseM;
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logic [`DIVBLEN:0] n, m;
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logic [`DIVBLEN:0] nE, nM, mM;
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logic OTFCSwap, ALTBM, As;
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logic OTFCSwapE, ALTBM, As;
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logic DivStartE;
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logic DivStartE;
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fdivsqrtpreproc fdivsqrtpreproc(
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fdivsqrtpreproc fdivsqrtpreproc(
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.clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
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.clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
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.Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc,
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.Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc,
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.n, .m, .OTFCSwap, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .As,
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.nE, .nM, .mM, .OTFCSwapE, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .As,
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
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fdivsqrtfsm fdivsqrtfsm(
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fdivsqrtfsm fdivsqrtfsm(
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.clk, .reset, .FmtE, .XsE, .SqrtE,
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.clk, .reset, .FmtE, .XsE, .SqrtE, .nE,
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.FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .FlushE, /*.DivDone, */
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.FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .FlushE, /*.DivDone, */
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.XZeroE, .YZeroE, .AZeroE, .BZeroE,
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.XZeroE, .YZeroE, .AZeroE, .BZeroE,
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.XNaNE, .YNaNE, .MDUE, .n,
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.XNaNE, .YNaNE, .MDUE,
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.XInfE, .YInfE, .WZeroM, .SpecialCaseM);
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.XInfE, .YInfE, .WZeroM, .SpecialCaseM);
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fdivsqrtiter fdivsqrtiter(
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fdivsqrtiter fdivsqrtiter(
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.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .MDUE, .SqrtE, // .SqrtM,
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.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .MDUE, .SqrtE, // .SqrtM,
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.X,.DPreproc, .FirstWS(WS), .FirstWC(WC),
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.X,.DPreproc, .FirstWS(WS), .FirstWC(WC),
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.IFDivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .OTFCSwap,
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.IFDivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .OTFCSwapE,
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.FDivBusyE);
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.FDivBusyE);
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fdivsqrtpostproc fdivsqrtpostproc(
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fdivsqrtpostproc fdivsqrtpostproc(
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.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
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.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
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.SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAE,
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.SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAE,
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.n, .ALTBM, .m, .BZeroM, .As,
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.nM, .ALTBM, .mM, .BZeroM, .As,
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.QmM, .WZeroM, .DivSM, .FPIntDivResultM);
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.QmM, .WZeroM, .DivSM, .FPIntDivResultM);
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endmodule
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endmodule
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@ -46,7 +46,7 @@ module fdivsqrtfsm(
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input logic FlushE,
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input logic FlushE,
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input logic WZeroM,
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input logic WZeroM,
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input logic MDUE,
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input logic MDUE,
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input logic [`DIVBLEN:0] n,
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input logic [`DIVBLEN:0] nE,
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output logic IFDivStartE,
|
output logic IFDivStartE,
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output logic FDivBusyE, FDivDoneE,
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output logic FDivBusyE, FDivDoneE,
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output logic SpecialCaseM
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output logic SpecialCaseM
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@ -104,7 +104,7 @@ module fdivsqrtfsm(
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always_comb begin
|
always_comb begin
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if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
|
if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
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else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
|
else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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cycles = MDUE ? n : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
|
cycles = MDUE ? nE : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
|
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end
|
end
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|
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/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
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|
@ -38,7 +38,7 @@ module fdivsqrtiter(
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input logic XZeroE, YZeroE,
|
input logic XZeroE, YZeroE,
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input logic SqrtE, MDUE,
|
input logic SqrtE, MDUE,
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// input logic SqrtM,
|
// input logic SqrtM,
|
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input logic OTFCSwap,
|
input logic OTFCSwapE,
|
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input logic [`DIVb+3:0] X,
|
input logic [`DIVb+3:0] X,
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input logic [`DIVb-1:0] DPreproc,
|
input logic [`DIVb-1:0] DPreproc,
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output logic [`DIVb-1:0] D,
|
output logic [`DIVb-1:0] D,
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@ -114,13 +114,13 @@ module fdivsqrtiter(
|
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generate
|
generate
|
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for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : iterations
|
for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : iterations
|
||||||
if (`RADIX == 2) begin: stage
|
if (`RADIX == 2) begin: stage
|
||||||
fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE, .OTFCSwap, .MDUE,
|
fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE, .OTFCSwapE, .MDUE,
|
||||||
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
|
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
|
||||||
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
|
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
|
||||||
end else begin: stage
|
end else begin: stage
|
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logic j1;
|
logic j1;
|
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assign j1 = (i == 0 & ~C[0][`DIVb-1]);
|
assign j1 = (i == 0 & ~C[0][`DIVb-1]);
|
||||||
fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1, .OTFCSwap, .MDUE,
|
fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1, .OTFCSwapE, .MDUE,
|
||||||
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
|
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
|
||||||
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
|
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
|
||||||
end
|
end
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|
@ -40,7 +40,7 @@ module fdivsqrtpostproc(
|
|||||||
input logic SpecialCaseM,
|
input logic SpecialCaseM,
|
||||||
input logic [`XLEN-1:0] ForwardedSrcAE,
|
input logic [`XLEN-1:0] ForwardedSrcAE,
|
||||||
input logic RemOpM, ALTBM, BZeroM, As,
|
input logic RemOpM, ALTBM, BZeroM, As,
|
||||||
input logic [`DIVBLEN:0] n, m,
|
input logic [`DIVBLEN:0] nM, mM,
|
||||||
output logic [`DIVb:0] QmM,
|
output logic [`DIVb:0] QmM,
|
||||||
output logic WZeroM,
|
output logic WZeroM,
|
||||||
output logic DivSM,
|
output logic DivSM,
|
||||||
@ -127,10 +127,10 @@ module fdivsqrtpostproc(
|
|||||||
|
|
||||||
always_comb
|
always_comb
|
||||||
if (RemOpM) begin
|
if (RemOpM) begin
|
||||||
NormShiftM = (m + (`DIVBLEN+1)'(`DIVa));
|
NormShiftM = (mM + (`DIVBLEN+1)'(`DIVa));
|
||||||
PreResultM = IntRemM;
|
PreResultM = IntRemM;
|
||||||
end else begin
|
end else begin
|
||||||
NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (n << `LOGR));
|
NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM << `LOGR));
|
||||||
PreResultM = {3'b000, IntQuotM};
|
PreResultM = {3'b000, IntQuotM};
|
||||||
end
|
end
|
||||||
|
|
||||||
|
@ -41,8 +41,8 @@ module fdivsqrtpreproc (
|
|||||||
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
||||||
input logic [2:0] Funct3E, Funct3M,
|
input logic [2:0] Funct3E, Funct3M,
|
||||||
input logic MDUE, W64E,
|
input logic MDUE, W64E,
|
||||||
output logic [`DIVBLEN:0] n, m,
|
output logic [`DIVBLEN:0] nE, nM, mM,
|
||||||
output logic OTFCSwap, ALTBM, As, AZeroM, BZeroM, AZeroE, BZeroE,
|
output logic OTFCSwapE, ALTBM, As, AZeroM, BZeroM, AZeroE, BZeroE,
|
||||||
output logic [`NE+1:0] QeM,
|
output logic [`NE+1:0] QeM,
|
||||||
output logic [`DIVb+3:0] X,
|
output logic [`DIVb+3:0] X,
|
||||||
output logic [`DIVb-1:0] DPreproc
|
output logic [`DIVb-1:0] DPreproc
|
||||||
@ -55,9 +55,9 @@ module fdivsqrtpreproc (
|
|||||||
// Intdiv signals
|
// Intdiv signals
|
||||||
logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
|
logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
|
||||||
logic [`XLEN-1:0] PosA, PosB;
|
logic [`XLEN-1:0] PosA, PosB;
|
||||||
logic Bs, CalcOTFCSwap, ALTBE;
|
logic Bs, CalcOTFCSwapE, ALTBE;
|
||||||
logic [`XLEN-1:0] A64, B64;
|
logic [`XLEN-1:0] A64, B64;
|
||||||
logic [`DIVBLEN:0] Calcn, Calcm;
|
logic [`DIVBLEN:0] mE;
|
||||||
logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
|
logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
|
||||||
logic [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
|
logic [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
|
||||||
logic [`LOGRK-1:0] pPrTrunc;
|
logic [`LOGRK-1:0] pPrTrunc;
|
||||||
@ -72,7 +72,7 @@ module fdivsqrtpreproc (
|
|||||||
assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
|
assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
|
||||||
assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE;
|
assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE;
|
||||||
|
|
||||||
assign CalcOTFCSwap = (As ^ Bs) & MDUE;
|
assign CalcOTFCSwapE = (As ^ Bs) & MDUE;
|
||||||
|
|
||||||
assign PosA = As ? -A64 : A64;
|
assign PosA = As ? -A64 : A64;
|
||||||
assign PosB = Bs ? -B64 : B64;
|
assign PosB = Bs ? -B64 : B64;
|
||||||
@ -82,19 +82,19 @@ module fdivsqrtpreproc (
|
|||||||
assign IFNormLenX = MDUE ? {PosA, {(`DIVb-`XLEN){1'b0}}} : {Xm, {(`DIVb-`NF-1){1'b0}}};
|
assign IFNormLenX = MDUE ? {PosA, {(`DIVb-`XLEN){1'b0}}} : {Xm, {(`DIVb-`NF-1){1'b0}}};
|
||||||
assign IFNormLenD = MDUE ? {PosB, {(`DIVb-`XLEN){1'b0}}} : {Ym, {(`DIVb-`NF-1){1'b0}}};
|
assign IFNormLenD = MDUE ? {PosB, {(`DIVb-`XLEN){1'b0}}} : {Ym, {(`DIVb-`NF-1){1'b0}}};
|
||||||
lzc #(`DIVb) lzcX (IFNormLenX, ell);
|
lzc #(`DIVb) lzcX (IFNormLenX, ell);
|
||||||
lzc #(`DIVb) lzcY (IFNormLenD, Calcm);
|
lzc #(`DIVb) lzcY (IFNormLenD, mE);
|
||||||
|
|
||||||
assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // had issue with (`DIVBLEN+1)'(~MDUE) so using this instead
|
assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // had issue with (`DIVBLEN+1)'(~MDUE) so using this instead
|
||||||
assign DPreproc = IFNormLenD << (Calcm + {{`DIVBLEN{1'b0}}, 1'b1}); // replaced ~MDUE with 1 bc we always want that extra left shift
|
assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); // replaced ~MDUE with 1 bc we always want that extra left shift
|
||||||
|
|
||||||
assign ZeroDiff = Calcm - ell;
|
assign ZeroDiff = mE - ell;
|
||||||
assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B
|
assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B
|
||||||
assign p = ALTBE ? '0 : ZeroDiff;
|
assign p = ALTBE ? '0 : ZeroDiff;
|
||||||
|
|
||||||
assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
|
assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
|
||||||
assign pPrTrunc = pPlusr[`LOGRK-1:0];
|
assign pPrTrunc = pPlusr[`LOGRK-1:0];
|
||||||
assign pPrCeil = (pPlusr >> `LOGRK) + {{`DIVBLEN{1'b0}}, |(pPrTrunc)};
|
assign pPrCeil = (pPlusr >> `LOGRK) + {{`DIVBLEN{1'b0}}, |(pPrTrunc)};
|
||||||
assign Calcn = (pPrCeil << `LOGK) - 1;
|
assign nE = (pPrCeil << `LOGK) - 1;
|
||||||
assign IntBits = (`DIVBLEN)'(`RK) + p;
|
assign IntBits = (`DIVBLEN)'(`RK) + p;
|
||||||
assign RightShiftX = (`DIVBLEN)'(`RK) - {{(`DIVBLEN-`RK){1'b0}}, IntBits[`RK-1:0]};
|
assign RightShiftX = (`DIVBLEN)'(`RK) - {{(`DIVBLEN-`RK){1'b0}}, IntBits[`RK-1:0]};
|
||||||
|
|
||||||
@ -119,14 +119,14 @@ module fdivsqrtpreproc (
|
|||||||
// DIVRESLEN/(r*`DIVCOPIES)
|
// DIVRESLEN/(r*`DIVCOPIES)
|
||||||
|
|
||||||
flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
|
flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
|
||||||
flopen #(1) swapreg(clk, IFDivStartE, CalcOTFCSwap, OTFCSwap);
|
flopen #(1) swapreg(clk, IFDivStartE, CalcOTFCSwapE, OTFCSwapE); // Retain value for each iteration of divider in Execute stage
|
||||||
flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
|
flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
|
||||||
flopen #(1) azeroreg(clk, IFDivStartE, AZeroE, AZeroM);
|
flopen #(1) azeroreg(clk, IFDivStartE, AZeroE, AZeroM);
|
||||||
flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
|
flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
|
||||||
flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, Calcn, n);
|
flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
|
||||||
flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, Calcm, m);
|
flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
|
||||||
//flopen #(`XLEN) srcareg(clk, IFDivStartE, ForwardedSrcAE, ForwardedSrcAM); //HERE
|
//flopen #(`XLEN) srcareg(clk, IFDivStartE, ForwardedSrcAE, ForwardedSrcAM); //HERE
|
||||||
expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZeroE, .ell, .m(Calcm), .Qe(QeE));
|
expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZeroE, .ell, .m(mE), .Qe(QeE));
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
@ -34,7 +34,7 @@ module fdivsqrtqsel4cmp (
|
|||||||
input logic [2:0] Dmsbs,
|
input logic [2:0] Dmsbs,
|
||||||
input logic [4:0] Smsbs,
|
input logic [4:0] Smsbs,
|
||||||
input logic [7:0] WSmsbs, WCmsbs,
|
input logic [7:0] WSmsbs, WCmsbs,
|
||||||
input logic SqrtE, j1, OTFCSwap, MDUE,
|
input logic SqrtE, j1, OTFCSwapE, MDUE,
|
||||||
output logic [3:0] udigit
|
output logic [3:0] udigit
|
||||||
);
|
);
|
||||||
logic [6:0] Wmsbs;
|
logic [6:0] Wmsbs;
|
||||||
@ -93,5 +93,5 @@ module fdivsqrtqsel4cmp (
|
|||||||
else udigitsel = 4'b0001; // choose -2
|
else udigitsel = 4'b0001; // choose -2
|
||||||
|
|
||||||
assign udigitswap = {udigitsel[0], udigitsel[1], udigitsel[2], udigitsel[3]};
|
assign udigitswap = {udigitsel[0], udigitsel[1], udigitsel[2], udigitsel[3]};
|
||||||
assign udigit = OTFCSwap ? udigitswap : udigitsel;
|
assign udigit = OTFCSwapE ? udigitswap : udigitsel;
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -38,7 +38,7 @@ module fdivsqrtstage2 (
|
|||||||
input logic [`DIVb+3:0] WS, WC,
|
input logic [`DIVb+3:0] WS, WC,
|
||||||
input logic [`DIVb+1:0] C,
|
input logic [`DIVb+1:0] C,
|
||||||
input logic SqrtE,
|
input logic SqrtE,
|
||||||
input logic OTFCSwap, MDUE,
|
input logic OTFCSwapE, MDUE,
|
||||||
output logic un,
|
output logic un,
|
||||||
output logic [`DIVb+1:0] CNext,
|
output logic [`DIVb+1:0] CNext,
|
||||||
output logic [`DIVb:0] UNext, UMNext,
|
output logic [`DIVb:0] UNext, UMNext,
|
||||||
@ -60,7 +60,7 @@ module fdivsqrtstage2 (
|
|||||||
// 0000 = 0
|
// 0000 = 0
|
||||||
// 0010 = -1
|
// 0010 = -1
|
||||||
// 0001 = -2
|
// 0001 = -2
|
||||||
fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], OTFCSwap, up, uz, un);
|
fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], OTFCSwapE, up, uz, un);
|
||||||
|
|
||||||
// Sqrt F generation
|
// Sqrt F generation
|
||||||
fdivsqrtfgen2 fgen2(.up, .uz, .C(CNext), .U, .UM, .F);
|
fdivsqrtfgen2 fgen2(.up, .uz, .C(CNext), .U, .UM, .F);
|
||||||
|
@ -36,7 +36,7 @@ module fdivsqrtstage4 (
|
|||||||
input logic [`DIVb:0] U, UM,
|
input logic [`DIVb:0] U, UM,
|
||||||
input logic [`DIVb+3:0] WS, WC,
|
input logic [`DIVb+3:0] WS, WC,
|
||||||
input logic [`DIVb+1:0] C,
|
input logic [`DIVb+1:0] C,
|
||||||
input logic SqrtE, j1, OTFCSwap, MDUE,
|
input logic SqrtE, j1, OTFCSwapE, MDUE,
|
||||||
output logic [`DIVb+1:0] CNext,
|
output logic [`DIVb+1:0] CNext,
|
||||||
output logic un,
|
output logic un,
|
||||||
output logic [`DIVb:0] UNext, UMNext,
|
output logic [`DIVb:0] UNext, UMNext,
|
||||||
@ -65,7 +65,7 @@ module fdivsqrtstage4 (
|
|||||||
assign WCmsbs = WC[`DIVb+3:`DIVb-4];
|
assign WCmsbs = WC[`DIVb+3:`DIVb-4];
|
||||||
assign WSmsbs = WS[`DIVb+3:`DIVb-4];
|
assign WSmsbs = WS[`DIVb+3:`DIVb-4];
|
||||||
|
|
||||||
fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit, .OTFCSwap, .MDUE);
|
fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit, .OTFCSwapE, .MDUE);
|
||||||
assign un = 1'b0; // unused for radix 4
|
assign un = 1'b0; // unused for radix 4
|
||||||
|
|
||||||
// F generation logic
|
// F generation logic
|
||||||
|
@ -114,7 +114,7 @@ module ifu (
|
|||||||
logic ICacheFetchLine;
|
logic ICacheFetchLine;
|
||||||
logic BusStall;
|
logic BusStall;
|
||||||
logic ICacheStallF, IFUCacheBusStallF;
|
logic ICacheStallF, IFUCacheBusStallF;
|
||||||
logic GatedStallF;
|
logic GatedStallD;
|
||||||
(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF;
|
(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF;
|
||||||
// branch predictor signal
|
// branch predictor signal
|
||||||
logic [`XLEN-1:0] PCNext1F, PCNext0F;
|
logic [`XLEN-1:0] PCNext1F, PCNext0F;
|
||||||
@ -200,7 +200,7 @@ module ifu (
|
|||||||
// The IROM uses untranslated addresses, so it is not compatible with virtual memory.
|
// The IROM uses untranslated addresses, so it is not compatible with virtual memory.
|
||||||
if (`IROM_SUPPORTED) begin : irom
|
if (`IROM_SUPPORTED) begin : irom
|
||||||
assign IFURWF = 2'b10;
|
assign IFURWF = 2'b10;
|
||||||
irom irom(.clk, .reset, .ce(~GatedStallF | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF));
|
irom irom(.clk, .reset, .ce(~GatedStallD | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF));
|
||||||
|
|
||||||
end else begin
|
end else begin
|
||||||
assign IFURWF = 2'b10;
|
assign IFURWF = 2'b10;
|
||||||
@ -222,7 +222,7 @@ module ifu (
|
|||||||
cache #(.LINELEN(`ICACHE_LINELENINBITS),
|
cache #(.LINELEN(`ICACHE_LINELENINBITS),
|
||||||
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
|
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
|
||||||
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
|
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
|
||||||
icache(.clk, .reset, .FlushStage(TrapM), .Stall(GatedStallF),
|
icache(.clk, .reset, .FlushStage(TrapM), .Stall(GatedStallD),
|
||||||
.FetchBuffer, .CacheBusAck(ICacheBusAck),
|
.FetchBuffer, .CacheBusAck(ICacheBusAck),
|
||||||
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
|
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
|
||||||
.CacheBusRW,
|
.CacheBusRW,
|
||||||
@ -244,7 +244,7 @@ module ifu (
|
|||||||
.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
|
.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
|
||||||
.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
|
.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
|
||||||
.FetchBuffer, .PAdr(PCPF),
|
.FetchBuffer, .PAdr(PCPF),
|
||||||
.BusRW, .Stall(GatedStallF),
|
.BusRW, .Stall(GatedStallD),
|
||||||
.BusStall, .BusCommitted(BusCommittedF));
|
.BusStall, .BusCommitted(BusCommittedF));
|
||||||
|
|
||||||
mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF),
|
mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF),
|
||||||
@ -261,7 +261,7 @@ module ifu (
|
|||||||
ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY),
|
ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY),
|
||||||
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
|
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
|
||||||
.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
|
.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
|
||||||
.Stall(GatedStallF), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
|
.Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
|
||||||
|
|
||||||
assign CacheCommittedF = '0;
|
assign CacheCommittedF = '0;
|
||||||
if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF);
|
if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF);
|
||||||
@ -278,7 +278,7 @@ module ifu (
|
|||||||
|
|
||||||
assign IFUCacheBusStallF = ICacheStallF | BusStall;
|
assign IFUCacheBusStallF = ICacheStallF | BusStall;
|
||||||
assign IFUStallF = IFUCacheBusStallF | SelNextSpillF;
|
assign IFUStallF = IFUCacheBusStallF | SelNextSpillF;
|
||||||
assign GatedStallF = StallF & ~SelNextSpillF;
|
assign GatedStallD = StallD & ~SelNextSpillF;
|
||||||
|
|
||||||
flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
|
flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user