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Removed two cycles of latency from the DTIM

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David Harris 2021-06-10 10:30:24 -04:00
parent 17b76d4cd7
commit c3d106f0f0
1 changed files with 1 additions and 1 deletions
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2
wally-pipelined/src/uncore/dtim.sv
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@ -69,7 +69,7 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
busycount <= 0; busycount <= 0;
HREADYTim <= #1 0; HREADYTim <= #1 0;
end else if (~HREADYTim) begin end else if (~HREADYTim) begin
if (busycount == 2) begin // TIM latency, for testing purposes. *** test with different values if (busycount == 0) begin // TIM latency, for testing purposes. *** test with different values such as 2
HREADYTim <= #1 1; HREADYTim <= #1 1;
end else begin end else begin
busycount <= busycount + 1; busycount <= busycount + 1;